Chapter 10
Motor Control PWM
X - 20 Operation
■ Setting PWM Period
The 3-phase period for PWMn is set by the PWM period setting register (PWMSETn). PWM counting is operated
by the PWMn binary counter (PWMBCn). The formula of the PWM period is as follows. The count clock of the
PWMBCn counter is IOCLK.
■ Starting and Stopping PWM Output
When the TCENn flag of the PWMMD0 register is set to “1”, PWM output starts and when set to “0”, it stops.
Table: 10.3.2 shows the PWM block status stopped.
Table:10.3.2 PWM Block Status When Counting Operation is Disabled
Waveform mode PWM period
Triangular wave Count clock period × (PWMSETn set value +1) × 2
Saw-tooth wave
Count clock period × (PWMSETn set value +1)
PWM block Status
Phase output
When positive polar-
ity is selected as out-
put polarity
PWMn0 to 2 L
NPWMn0 to 2 H
When negative polar-
ity is selected as out-
put polarity
PWMn0 to 2 H
NPWMn0 to 2 L
PWM binary counter (16-bit counter) Undefined
Dead Time counter Reset status
PWM control register (double-buffer) Double-buffer data loaded
PWM control register (single-buffer) Retained
To Next Page
Loading...
