Panasonic MN103S

Chapter 13
Serial Interface 2
Operation XIII - 21
Figure:13.3.11 Reception Timing (Falling Edge, With Start Condition)
Figure:13.3.12 Reception Timing (Falling Edge, Without Start Condition)
T
01234567
T
SC2RBSY
Interrupt
(SC2TIRQ)
Clock
(SBT2 pin)
Input pin
(SBO2 pin)
Transfer bit
counter
T
01234567
At master
Tmax=3.5T
SC2RBSY
(Data set to SC2TB)
Interrupt
(SC2TIRQ)
Clock
(SBT2 pin)
Input pin
(SBO2 pin)
Transfer bit
counter