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Panasonic MN103S

Panasonic MN103S
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Chapter 1
Overview
I - 24 Electrical Characteristics
Figure:1.5.4 Interrupt signal timing
Interrupt signal input timing
V
DD
=5.0 V
V
SS
= 0.0 V
Ta= -40 °C to +85 °C
CL= 50 pF
Tmclk = 1/MCLK
Tsmp = n/IOCLK
n = 4,8 ,16,32
Parameter Symbol Conditions
Limits
Unit
Min. Typ. Max.
E3 Interrupt signal pulse width(IRQn)
In not using noise filter
tlRQW1 -
Tmclk x 3
*1
*1.When no noise filter is used, the minimum pulse width is determined by system clock(MCLK). Maintain the interrupt signal for a
minimum of 3 cycles of MCLK.
--ns
E4 Interrupt signal pulse width(IRQn)
In using noise filter
tlRQW2 -
Tsmp x 3
*2
*2.When noise filter is used, the minimum pulse width is determined by sampling clock. Maintain the interrupt signal for a minimum of
3 cycles of sampling clock. Refer to [5-4-7 Noise Filter Operation] for further details.
--ns
tIRQW1, tIRQW2
IRQ

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