Panasonic MN103S

Chapter 16
Appendix
Instruction Set XVI - 29
MN1030/MN103S SERIES INSTRUCTION SET
INSTRUCTION SET  Description Dn,Dm,Di data registers An,Am address registers MDR multiply/divide register PSW processor status word PC program counter SP stack pointer LIR loop instruction registers LAR loop address registers imm8,imm16,imm32 immediate value(8, 16 or 32 bits) d8,d16,d32 displacement(8, 16 or 32 bits) abs16,abs32 absolute address (16 or 32 bits) mem8(An) lower 8-bit data in memory referred by () address mem16(An) lower 16bit data in memory referred by ()address mem32(An) lower 32-bit data in memory referred by () address regs registers .lsb,.msb bit location(lowest/highest) & logical AND | logical OR ^ exclusive OR ~ bit inverted op operation defined by users <<,>> bit shift(right/left) performsa bit shift for specified value VF overflow flags CF carry flags NF negative flags ZF zero flags temp temporary registers → move : reflects operation result (sign_ext) sign-extend (zero_ext) zero-extend {MDR,Dn} 64-bit data defined whose upper 32-bit data are in MDR and lower 32-bit in register Dn within "{}". 0x.... hexadecimal(hexadecimal following to 0x.)
 Flag z changes - no changes 0 always 0 1 alwayas 1 ? not defined * defined by users  CodeSize byte:  Cycles Cycles may be changed the status of the pipline, memory space to access. Cycles are calculated on those conditions; (1) no pipeline installation (2) Instruction queue: 2 cycles data load/store: 1 cycle (ROM/RAM/ internal flash: Instructions: access to internal ROM/RAM space data: access to internal RAM space with cache Instructions/data :access to cachable area and hit the chache) Please see the LSI manuals for how the pipeline installation affects the cycles. If using extended instructions, the users define the cycles.  Format Please refer to “Chapter 1, 6 Instruction Formats” in MN1030/MN103S Instruction Manual.
 IInstructions replaced to other instructions by Assembler Format or Mchine Codeare not written usable CodeSize and Cycles are written MOVB Reg,Mem , MOVH Reg,Mem, ASR Dn , LSR Dn , RTS  Instructions replaced to multiple instructions by Assembler Format or Mchine Code are not written usable CodeSize and Cycles are written MOVB Mem,Reg , MOVH Reg,Mem , JSR (An) , JSR label