Panasonic MN103S

Chapter 16
Appendix
XVI - 40 Extension Instruction Specification
The following shows symbols used in flag change tables:
..
Low-order 4 bits (V, C, N, Z) of PSW are collectively called “flags”.
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■ Extension arithmetic unit register set
Each of the extension arithmetic units has the following dedicated registers to store high-speed multiply and
multiply and accumulate results:
Figure:16.4.2 Extension Arithmetic Unit Register Set
Multiply register (one 32-bit register)
This register is provided for high-speed multiply instruction and stores high-order 32 bits of multiply result that is
64 bits long when multiply instruction is used.
Multiply and accumulate register (higher) (one 32-bit register)
This register is provided for multiply and accumulate instructions and stores high-order 32 bits of multiply and
accumulate result that is 64 bits long when multiply and accumulate instruction is used.
Multiply and accumulate register (lower) (one 32-bit register)
This register is provided for multiply and accumulate instruction and stores low-order 32 bits of multiply and
accumulate result that is 64 bits long when multiply and accumulate instruction is used.
Multiply and accumulate overflow detection flag register (one 1-bit register)
This register is set when an overflow occurs as a result of execution of multiply and accumulate instruction and is
not cleared until the next CLRMAC or PUTCX instruction is executed.
- : Flag unchanged
+ : Flag changed
* : Undefined
0 : Reset
1 : Set
MDRQ
MCRH
MCRL
MCVF
031
31
31
0
0
0
Multiply Register
Multiply & Accumulate
Multiply & Accumulate
Overflow Detect Flag Register
Register(Lower)
Multiply & Accumulate
Register(Higher)