Chapter 16
Appendix
XVI - 48 Extension Instruction Specification
MULQU (unsigned high-speed multiply instruction: register to register)
[Instruction format (macro name)]
MULQU Dm, Dn
[Assembler mnemonic]
udf01 Dm, Dn
[Operation]
This instruction performs high-speed multiply operation by means of the multiplier provided in the extension
arithmetic unit.
The instruction multiplies the content of Dm (unsigned 32-bit integer: multiplicand) by the content of Dn
(unsigned 32-bit integer: multiplier) and stores high-order 32 bits and low-order 32 bits of the 64-bit result
respectively in the high-speed multiply register MDRQ and Dn.
The instruction determines the range within which the multiplier stored in Dn is significant (determination is
made starting LSB and in units of 2 bytes) before performing operation. Only the range within which a significant
value is contained is subject to multiply operation. That is, the smaller the content of Dn, the faster the operation
result is obtained.
[Flag changes]
[Note for programming]
Updating of the PSW as a result of flag changes is delayed by 1 instruction.
Note, however, that flags can be evaluated for the Bcc and Lcc instructions before flag changes are reflected in the
PSW.
Flag Change Condition
V * Undefined
C * Undefined
N + "1" if the MSB of the low-order 32 bits of the result is "1." "0" in any other case.
Z + "1" if the low-order 32 bits of the result are "0s." "0" in any other case.
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