Record of Changes - 5
XIII-3 Figure
13.1.1
Change
XIII-4 Note Add - Whe changing the setting value ... registers
are set to “0“.)
XIII-7 bp7 Change
SC2IOM Serial data input selection SC2IOM Serial data input pin selection
bp5 Change
SC2SBIS 0: ”1” input
1: Serial input
SC2SBIS 0: ”1” input fix
1: Serial data input
Note Add - Whe changing the setting value ... registers
are set to “0“.)
XIII-11 Activati
on
Factors
for
Commu-
nication
Change However, the external clock should be fed
after more than 2.5
transfer clock ...
However, the external clock should be fed after
more than 3.5 transfer clock ...
Transmi
ssion
Data
Buffer
Change ... into the internal
shift register. ... into the
internal shift register. 2.5
transfer clock cycles
...
... into the transmission
shift register. ... into
the internal shift register. 3.5
transfer clock
cycles ...
XIII
-12
Recepti
on Data
Buffer
Change ... the received data by the internal
shift regis-
ter. After the communication complete inter-
rupt SC2TIRQ is generated, data stored in the
internal
shift register ...
... the received data by the reception
shift reg-
ister. After the communication complete inter-
rupt SC2TIRQ is generated, data stored in the
reception
shift register ...
Note 4 Change Wait more than 2.5
transfer clocks for ... Wait more than 3.5 transfer clocks for ...
Setting
Start
Condition
Change ... before change the start condition edge. ... before change the start condition edge.
Then, select "without start condition" when
performing transmission and reception at the
same time. It may not be operated properly.
XIII
-15
Table
13.3.4
Change
At slave [1-bit data length of external clock x
1/2]+[Internal clock cycle x (1 to 2)]
At slave [1-bit data length of external clock x
1/2]+[Internal clock cycle x (1/2 to 3/2)]
XIII
-16
Note Add - In using synchronous serial interface, ...
GI5IR0 is not generated.
Recepti
on Buffer
Empty
Flag
Operation
Change ... stored from the internal
shift register into
SC2RB. ...
... stored from the reception shift register into
SC2RB. ...
Transmi
ssion
Buffer
Empty
Flag
Operation
Change ... is generated after data is load into the inter-
nal shift register), ...
... is generated after data is load into the trans-
mission shift register), ...
Page Section Definition Previous Edition (Ver.1.1) New Edition (Ver.1.2)
Reception
shift register
Transmission
shift register
M
M
U
X
SC2STE
SC2CMD
SC2RDB
SC2TRB
Reception
buffer
SC2DIR
Read/Write
SC2RB
SC2TB
SWAP MSB<->LSB
Start condition
generation circuit
Transmission
control circuit
Transmission
buffer
Start condition
detection circuit
Reception
shift register
Transmission
shift register
M
U
X
SC2STE
SC2CMD
SC2RDB
SC2TRB
Reception
data buffer
SC2DIR
Read/Write
SC2RB
SC2TB
SWAP MSB<->LSB
Start condition
generation circuit
Transmission
control circuit
Transmission
data buffer
Start condition
detection circuit
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