Chapter 4
Bus Controller
Operation IV - 7
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When the CPU clock (MCLK) is 40 MHz or over, change an access to the internal ROM to 3
cycle access (ROMMC[1:0]=10) by the internal ROM access control register (ROMCTR)
before the PLLSEL flag of the PLL control register (PCNT) is switched "0" to "1".
The operation that is set to 2 cycle access is not guranteed.
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When the PLLON and CKSEL [1:0] flags of the PCNT register are changed, reset the PLLSEL flag to
“0” before the change and set to “1” after waiting over 200 µs.
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