Philips LPC2101 - Page 268

Philips Semiconductors
UM10161
Volume 1 Chapter 22: Supplementary information
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 268
continued >>
Table 100:UART1 Transmitter Holding Register (U1THR -
address 0xE001 0000, when DLAB = 0 Write
Only) bit description . . . . . . . . . . . . . . . . . . . .101
Table 101:UART1 Divisor Latch LSB register (U1DLL -
address 0xE001 0000, when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Table 102:UART1 Divisor Latch MSB register (U1DLM -
address 0xE001 0004, when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .102
Table 103:UART1 Fractional Divider Register (U1FDR -
address 0xE001 0028) bit description . . . . . .102
Table 104:Baudrates available when using 20 MHz
peripheral clock (PCLK = 20 MHz) . . . . . . . . .103
Table 105:UART1 Interrupt Enable Register (U1IER -
address 0xE001 0004, when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .104
Table 106:UART1 Interrupt Identification Register (U1IIR -
address 0xE001 0008, read only) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .105
Table 107:UART1 interrupt handling . . . . . . . . . . . . . . . .107
Table 108:UART1 FIFO Control Register (U1FCR - address
0xE001 0008) bit description . . . . . . . . . . . . .108
Table 109:UART1 Line Control Register (U1LCR - address
0xE001 000C) bit description . . . . . . . . . . . . .108
Table 110:UART1 Modem Control Register (U1MCR -
address 0xE001 0010) bit description . . . . . .109
Table 111:Modem status interrupt generation. . . . . . . . .110
Table 112:UART1 Line Status Register (U1LSR - address
0xE001 0014, read only) bit description . . . . .111
Table 113:UART1 Modem Status Register (U1MSR -
address 0xE001 0018) bit description . . . . . .113
Table 114:UART1 Scratch Pad Register (U1SCR - address
0xE001 0014) bit description . . . . . . . . . . . . .113
Table 115:Auto-baud Control Register (U1ACR -
0xE001 0020) bit description . . . . . . . . . . . . .113
Table 116:UART1 Transmit Enable Register (U1TER -
address 0xE001 0030) bit description . . . . . .117
Table 117:I
2
C Pin Description . . . . . . . . . . . . . . . . . . . . .120
Table 118:I2C0CONSET and I2C1CONSET used to
configure Master mode. . . . . . . . . . . . . . . . . .121
Table 119:I2C0CONSET and I2C1CONSET used to
configure Slave mode . . . . . . . . . . . . . . . . . . .122
Table 120:I
2
C register map . . . . . . . . . . . . . . . . . . . . . . .127
Table 121:I
2
C Control Set register (I2CONSET: I2C0,
I2C0CONSET - address 0xE001 C000 and I2C1,
I2C1CONSET - address 0xE005 C000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .128
Table 122:I
2
C Control Set register (I2CONCLR: I2C0,
I2C0CONCLR - address 0xE001 C018 and I2C1,
I2C1CONCLR - address 0xE005 C018) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .130
Table 123:I
2
C Status register (I2STAT: I2C0, I2C0STAT -
address 0xE001 C004 and I2C1, I2C1STAT -
address 0xE005 C004) bit description . . . . . . 130
Table 124:I
2
C Data register (I2DAT: I2C0, I2C0DAT - address
0xE001 C008 and I2C1, I2C1DAT - address
0xE005 C008) bit description. . . . . . . . . . . . . 131
Table 125:I
2
C Slave Address register (I2ADR: I2C0,
I2C0ADR - address 0xE001 C00C and I2C1,
I2C1ADR - address 0xE005 C00C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 126:I
2
C SCL HIGH Duty Cycle register (I2SCLH: I2C0,
I2C0SCLH - address 0xE001 C010 and I2C1,
I2C1SCLH - address 0xE005 C010) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 127:I
2
C SCL Low Duty Cycle register (I2SCLL: I2C0,
I2C0SCLL - address 0xE001 C014 and I2C1,
I2C1SCLL - address 0xE005 C014) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 128:Example I
2
C clock rates. . . . . . . . . . . . . . . . . 132
Table 129:Abbreviations used to describe an I
2
C
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 130:I2CONSET used to initialize Master Transmitter
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 131:I2C0ADR and I2C1ADR usage in Slave Receiver
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 132:I2C0CONSET and I2C1CONSET used to initialize
Slave Receiver mode . . . . . . . . . . . . . . . . . . . 134
Table 133:Master Transmitter mode . . . . . . . . . . . . . . . . 140
Table 134:Master Receiver mode . . . . . . . . . . . . . . . . . . 141
Table 135:Slave Receiver mode . . . . . . . . . . . . . . . . . . . 142
Table 136:Slave Transmitter mode . . . . . . . . . . . . . . . . . 144
Table 137:Miscellaneous States . . . . . . . . . . . . . . . . . . . 146
Table 138:SPI data to clock phase relationship . . . . . . . 158
Table 139:SPI pin description . . . . . . . . . . . . . . . . . . . . . 161
Table 140:SPI register map . . . . . . . . . . . . . . . . . . . . . . 162
Table 141:SPI Control Register (S0SPCR - address
0xE002 0000) bit description . . . . . . . . . . . . . 162
Table 142:SPI Status Register (S0SPSR - address
0xE002 0004) bit description . . . . . . . . . . . . . 163
Table 143:SPI Data Register (S0SPDR - address
0xE002 0008) bit description . . . . . . . . . . . . . 164
Table 144:SPI Clock Counter Register (S0SPCCR - address
0xE002 000C) bit description. . . . . . . . . . . . . 164
Table 145:SPI Interrupt register (S0SPINT - address
0xE002 001C) bit description. . . . . . . . . . . . . 164
Table 146:SSP pin descriptions . . . . . . . . . . . . . . . . . . . 166
Table 147:SSP register map. . . . . . . . . . . . . . . . . . . . . . 175
Table 148:SSP Control Register 0 (SSPCR0 - address
0xE006 8000) bit description . . . . . . . . . . . . . 175
Table 149:SSP Control Register 1 (SSPCR1 - address
0xE006 8004) bit description . . . . . . . . . . . . . 176