Philips LPC2101 - Page 267

Philips Semiconductors
UM10161
Volume 1 Chapter 22: Supplementary information
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 267
continued >>
0xFFFF F000) bit allocation . . . . . . . . . . . . . . .50
Table 49: IRQ Status register (VICIRQStatus - address
0xFFFF F000) bit description . . . . . . . . . . . . . .50
Table 50: FIQ Status register (VICFIQStatus - address
0xFFFF F004) bit allocation . . . . . . . . . . . . . . .51
Table 51: FIQ Status register (VICFIQStatus - address
0xFFFF F004) bit description . . . . . . . . . . . . . .51
Table 52: Vector Control registers 0-15 (VICVectCntl0-15 -
0xFFFF F200-23C) bit description . . . . . . . . . .51
Table 53: Vector Address registers (VICVectAddr0-15 -
addresses 0xFFFF F100-13C) bit description .52
Table 54: Default Vector Address register (VICDefVectAddr
- address 0xFFFF F034) bit description . . . . . .52
Table 55: Vector Address register (VICVectAddr - address
0xFFFF F030) bit description . . . . . . . . . . . . . .52
Table 56: Protection Enable register (VICProtection -
address 0xFFFF F020) bit description . . . . . . .52
Table 57: Connection of interrupt sources to the Vectored
Interrupt Controller (VIC) . . . . . . . . . . . . . . . . .53
Table 58: Pin description . . . . . . . . . . . . . . . . . . . . . . . . .61
Table 59: Pin connect block register map. . . . . . . . . . . . .66
Table 60: Pin function select register 0 (PINSEL0 -
0xE002 C000) . . . . . . . . . . . . . . . . . . . . . . . . .67
Table 61: Pin function select register 1 (PINSEL1 -
0xE002 C004) . . . . . . . . . . . . . . . . . . . . . . . . .68
Table 62: Pin function select register bits. . . . . . . . . . . . .70
Table 63: GPIO pin description . . . . . . . . . . . . . . . . . . . .71
Table 64: GPIO register map (legacy APB accessible
registers). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Table 65: GPIO register map (local bus accessible registers
- enhanced GPIO features). . . . . . . . . . . . . . . .73
Table 66: GPIO port 0 Direction register (IO0DIR - address
0xE002 8008) bit description . . . . . . . . . . . . . .73
Table 67: Fast GPIO port 0 Direction register (FIO0DIR -
address 0x3FFF C000) bit description . . . . . . .74
Table 68: Fast GPIO port 0 Direction control byte and
half-word accessible register description . . . . .74
Table 69: Fast GPIO port 0 Mask register (FIO0MASK -
address 0x3FFF C010) bit description . . . . . . .74
Table 70: Fast GPIO port 0 Mask byte and half-word
accessible register description . . . . . . . . . . . . .75
Table 71: GPIO port 0 Pin value register (IO0PIN - address
0xE002 8000) bit description . . . . . . . . . . . . . .76
Table 72: Fast GPIO port 0 Pin value register (FIO0PIN -
address 0x3FFF C014) bit description . . . . . . .76
Table 73: Fast GPIO port 0 Pin value byte and half-word
accessible register description . . . . . . . . . . . . .76
Table 74: GPIO port 0 output Set register (IO0SET -
address 0xE002 8004 bit description . . . . . . . .77
Table 75: Fast GPIO port 0 output Set register (FIO0SET -
address 0x3FFF C018) bit description . . . . . . .77
Table 76: Fast GPIO port 0 output Set byte and half-word
accessible register description. . . . . . . . . . . . . 77
Table 77: GPIO port 0 output Clear register 0 (IO0CLR -
address 0xE002 800C) bit description . . . . . . . 77
Table 78: Fast GPIO port 0 output Clear register 0
(FIO0CLR - address 0x3FFF C01C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 79: Fast GPIO port 0 output Clear byte and half-word
accessible register description. . . . . . . . . . . . . 78
Table 80: UART0 pin description . . . . . . . . . . . . . . . . . . . 82
Table 81: UART0 register map . . . . . . . . . . . . . . . . . . . . 83
Table 82: UART0 Receiver Buffer Register (U0RBR -
address 0xE000 C000, when DLAB = 0, Read
Only) bit description . . . . . . . . . . . . . . . . . . . . 84
Table 83: UART0 Transmit Holding Register (U0THR -
address 0xE000 C000, when DLAB = 0, Write
Only) bit description . . . . . . . . . . . . . . . . . . . . . 84
Table 84: UART0 Divisor Latch LSB register (U0DLL -
address 0xE000 C000, when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 85: UART0 Divisor Latch MSB register (U0DLM -
address 0xE000 C004, when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 86: UART0 Fractional Divider Register (U0FDR -
address 0xE000 C028) bit description . . . . . . . 85
Table 87: Baudrates available when using 20 MHz
peripheral clock (PCLK = 20 MHz). . . . . . . . . . 86
Table 88: UART0 Interrupt Enable Register (U0IER -
address 0xE000 C004, when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 89: UART0 Interrupt Identification Register (UOIIR -
address 0xE000 C008, read only) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 90: UART0 interrupt handling. . . . . . . . . . . . . . . . . 89
Table 91: UART0 FIFO Control Register (U0FCR - address
0xE000 C008) bit description. . . . . . . . . . . . . . 90
Table 92: UART0 Line Control Register (U0LCR - address
0xE000 C00C) bit description . . . . . . . . . . . . . 90
Table 93: UART0 Line Status Register (U0LSR - address
0xE000 C014, read only) bit description . . . . . 91
Table 94: UART0 Scratch Pad Register (U0SCR - address
0xE000 C01C) bit description . . . . . . . . . . . . . 92
Table 95: Auto-baud Control Register (U0ACR -
0xE000 C020) bit description. . . . . . . . . . . . . . 93
Table 96: UART0 Transmit Enable Register (U0TER -
address 0xE000 C030) bit description . . . . . . . 94
Table 97: UART1 pin description . . . . . . . . . . . . . . . . . . . 99
Table 98: UART1 register map . . . . . . . . . . . . . . . . . . . 100
Table 99: UART1 Receiver Buffer Register (U1RBR -
address 0xE001 0000, when DLAB = 0 Read
Only) bit description . . . . . . . . . . . . . . . . . . . 101