Philips Semiconductors
UM10161
Volume 1 Chapter 22: Supplementary information
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 274
continued >>
8.4.2 Fast GPIO port 0 Mask register (FIOMASK,
Port 0: FIO0MASK - 0x3FFF C010) . . . . . . . . 74
8.4.3 GPIO port 0 Pin value register (IOPIN, Port 0:
IO0PIN - 0xE002 8000; FIOPIN, Port 0: FIO0PIN
- 0x3FFF C014) . . . . . . . . . . . . . . . . . . . . . . . 75
8.4.4 GPIO port 0 output Set register (IOSET, Port 0:
IO0SET - 0xE002 8004; FIOSET, Port 0:
FIO0SET - 0x3FFF C018) . . . . . . . . . . . . . . . 76
8.4.5 GPIO port 0 output Clear register (IOCLR, Port 0:
IO0CLR - 0xE002 800C; FIOCLR, Port 0:
FIO0CLR - 0x3FFF C01C) . . . . . . . . . . . . . . . 77
8.5 GPIO usage notes . . . . . . . . . . . . . . . . . . . . . . 78
8.5.1 Example 1: sequential accesses to IOSET and
IOCLR affecting the same GPIO pin/bit . . . . . 78
8.5.2 Example 2: an immediate output of 0s and 1s on
a GPIO port . . . . . . . . . . . . . . . . . . . . . . . . . . 79
8.5.3 Writing to IOSET/IOCLR vs. IOPIN . . . . . . . . 79
8.5.4 Output signal frequency considerations when
using the legacy and enhanced GPIO
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Chapter 9: Universal Asynchronous Receiver/Transmitter 0 (UART0)
9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9.2 Pin description. . . . . . . . . . . . . . . . . . . . . . . . . 82
9.3 Register description . . . . . . . . . . . . . . . . . . . . 82
9.3.1 UART0 Receiver Buffer register (U0RBR -
0xE000 C000, when DLAB = 0, Read Only). . 84
9.3.2 UART0 Transmit Holding Register (U0THR -
0xE000 C000, when DLAB = 0, Write Only). . 84
9.3.3 UART0 Divisor Latch registers (U0DLL -
0xE000 C000 and U0DLM - 0xE000 C004, when
DLAB = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
9.3.4 UART0 Fractional Divider Register (U0FDR -
0xE000 C028). . . . . . . . . . . . . . . . . . . . . . . . . 85
9.3.5 UART0 baudrate calculation . . . . . . . . . . . . . . 86
9.3.6 UART0 Interrupt Enable Register (U0IER -
0xE000 C004, when DLAB = 0) . . . . . . . . . . . 87
9.3.7 UART0 Interrupt Identification Register (U0IIR -
0xE000 C008, Read Only) . . . . . . . . . . . . . . . 88
9.3.8 UART0 FIFO Control Register (U0FCR -
0xE000 C008) . . . . . . . . . . . . . . . . . . . . . . . . 90
9.3.9 UART0 Line Control Register (U0LCR -
0xE000 C00C) . . . . . . . . . . . . . . . . . . . . . . . . 90
9.3.10 UART0 Line Status Register (U0LSR -
0xE000 C014, Read Only) . . . . . . . . . . . . . . . 91
9.3.11 UART0 Scratch Pad Register (U0SCR -
0xE000 C01C) . . . . . . . . . . . . . . . . . . . . . . . . 92
9.3.12 UART0 Auto-baud Control Register (U0ACR -
0xE000 C020) . . . . . . . . . . . . . . . . . . . . . . . . 93
9.3.13 Auto-baud. . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
9.3.14 UART0 Transmit Enable Register (U0TER -
0xE000 C030) . . . . . . . . . . . . . . . . . . . . . . . . 94
9.3.15 Auto-baud modes. . . . . . . . . . . . . . . . . . . . . . 95
9.4 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Chapter 10: Universal Asynchronous Receiver/Transmitter 1 (UART1)
10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
10.2 Pin description. . . . . . . . . . . . . . . . . . . . . . . . . 99
10.3 Register description . . . . . . . . . . . . . . . . . . . . 99
10.3.1 UART1 Receiver Buffer Register (U1RBR -
0xE001 0000, when DLAB = 0 Read Only) . 101
10.3.2 UART1 Transmitter Holding Register (U1THR -
0xE001 0000, when DLAB = 0 Write Only) . 101
10.3.3 UART1 Divisor Latch registers 0 and 1 (U1DLL -
0xE001 0000 and U1DLM - 0xE001 0004, when
DLAB = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 101
10.3.4 UART1 Fractional Divider Register (U1FDR -
0xE001 0028) . . . . . . . . . . . . . . . . . . . . . . . . 102
10.3.5 UART1 baudrate calculation. . . . . . . . . . . . . 103
10.3.6 UART1 Interrupt Enable Register (U1IER -
0xE001 0004, when DLAB = 0) . . . . . . . . . . 104
10.3.7 UART1 Interrupt Identification Register (U1IIR -
0xE001 0008, Read Only) . . . . . . . . . . . . . . 105
10.3.8 UART1 FIFO Control Register (U1FCR -
0xE001 0008). . . . . . . . . . . . . . . . . . . . . . . . 107
10.3.9 UART1 Line Control Register (U1LCR -
0xE001 000C) . . . . . . . . . . . . . . . . . . . . . . . 108
10.3.10 UART1 Modem Control Register (U1MCR -
0xE001 0010). . . . . . . . . . . . . . . . . . . . . . . . 109
10.3.11 UART1 Line Status Register (U1LSR -
0xE001 0014, Read Only) . . . . . . . . . . . . . . 111
10.3.12 UART1 Modem Status Register (U1MSR -
0xE001 0018). . . . . . . . . . . . . . . . . . . . . . . . 112
10.3.13 UART1 Scratch Pad Register (U1SCR -
0xE001 001C) . . . . . . . . . . . . . . . . . . . . . . . 113
10.3.14 UART1 Auto-baud Control Register (U1ACR -
0xE001 0020). . . . . . . . . . . . . . . . . . . . . . . . 113
10.3.15 Auto-baud. . . . . . . . . . . . . . . . . . . . . . . . . . . 114
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