Philips LPC2101 - Page 275

Philips Semiconductors
UM10161
Volume 1 Chapter 22: Supplementary information
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
User manual Rev. 01 — 12 January 2006 275
continued >>
10.3.16 Auto-baud modes . . . . . . . . . . . . . . . . . . . . . 115
10.3.17 UART1 Transmit Enable Register (U1TER -
0xE001 0030) . . . . . . . . . . . . . . . . . . . . . . . . 116
10.4 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Chapter 11: I
2
C interfaces I
2
C0 and I
2
C1
11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
11.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . 119
11.3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
11.4 Pin description. . . . . . . . . . . . . . . . . . . . . . . . 120
11.5 I
2
C operating modes . . . . . . . . . . . . . . . . . . . 120
11.5.1 Master Transmitter mode . . . . . . . . . . . . . . . 120
11.5.2 Master Receiver mode . . . . . . . . . . . . . . . . . 121
11.5.3 Slave Receiver mode . . . . . . . . . . . . . . . . . . 122
11.5.4 Slave Transmitter mode . . . . . . . . . . . . . . . . 123
11.6 I
2
C implementation and operation . . . . . . . . 123
11.6.1 Input filters and output stages . . . . . . . . . . . 123
11.6.2 Address Register, I2ADDR . . . . . . . . . . . . . . 125
11.6.3 Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . 125
11.6.4 Shift register, I2DAT . . . . . . . . . . . . . . . . . . . 125
11.6.5 Arbitration and synchronization logic . . . . . . 125
11.6.6 Serial clock generator. . . . . . . . . . . . . . . . . . 126
11.6.7 Timing and control . . . . . . . . . . . . . . . . . . . . 126
11.6.8 Control register, I2CONSET and I2CONCLR 127
11.6.9 Status decoder and status register. . . . . . . . 127
11.7 Register description . . . . . . . . . . . . . . . . . . . 127
11.7.1 I
2
C Control Set register (I2CONSET: I2C0,
I2C0CONSET - 0xE001 C000 and I2C1,
I2C1CONSET - 0xE005 C000). . . . . . . . . . . 128
11.7.2 I
2
C Control Clear register (I2CONCLR: I2C0,
I2C0CONCLR - 0xE001 C018 and I2C1,
I2C1CONCLR - 0xE005 C018). . . . . . . . . . . 130
11.7.3 I
2
C Status register (I2STAT: I2C0, I2C0STAT -
0xE001 C004 and I2C1, I2C1STAT -
0xE005 C004). . . . . . . . . . . . . . . . . . . . . . . . 130
11.7.4 I
2
C Data register (I2DAT: I2C0, I2C0DAT -
0xE001 C008 and I2C1,
I2C1DAT - 0xE005 C008) . . . . . . . . . . . . . . . 131
11.7.5 I
2
C Slave Address register (I2ADR: I2C0,
I2C0ADR - 0xE001 C00C and I2C1, I2C1ADR -
address 0xE005 C00C) . . . . . . . . . . . . . . . . 131
11.7.6 I
2
C SCL HIGH duty cycle register (I2SCLH: I2C0,
I2C0SCLH - 0xE001 C010 and I2C1, I2C1SCLH -
0xE0015 C010). . . . . . . . . . . . . . . . . . . . . . . 131
11.7.7 I
2
C SCL Low duty cycle register (I2SCLL: I2C0 -
I2C0SCLL: 0xE001 C014; I2C1 - I2C1SCLL:
0xE0015 C014). . . . . . . . . . . . . . . . . . . . . . . 131
11.7.8 Selecting the appropriate I
2
C data rate and duty
cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
11.8 Details of I
2
C operating modes . . . . . . . . . . 132
11.8.1 Master Transmitter mode . . . . . . . . . . . . . . . 133
11.8.2 Master Receiver mode . . . . . . . . . . . . . . . . . 134
11.8.3 Slave Receiver mode . . . . . . . . . . . . . . . . . . 134
11.8.4 Slave Transmitter mode . . . . . . . . . . . . . . . . 139
11.8.5 Miscellaneous states . . . . . . . . . . . . . . . . . . 145
11.8.6 I2STAT = 0xF8 . . . . . . . . . . . . . . . . . . . . . . . 145
11.8.7 I2STAT = 0x00 . . . . . . . . . . . . . . . . . . . . . . . 145
11.8.8 Some special cases . . . . . . . . . . . . . . . . . . . 146
11.8.9 Simultaneous repeated START conditions from
two masters . . . . . . . . . . . . . . . . . . . . . . . . . 146
11.8.10 Data transfer after loss of arbitration . . . . . . 146
11.8.11 Forced access to the I
2
C-bus. . . . . . . . . . . . 146
11.8.12 I
2
C-bus obstructed by a LOW level on SCL or
SDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.8.13 Bus error . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
11.8.14 I
2
C state service routines. . . . . . . . . . . . . . . 148
11.8.15 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 148
11.8.16 I
2
C interrupt service . . . . . . . . . . . . . . . . . . . 149
11.8.17 The state service routines . . . . . . . . . . . . . . 149
11.8.18 Adapting state services to an application. . . 149
11.9 Software example . . . . . . . . . . . . . . . . . . . . . 149
11.9.1 Initialization routine . . . . . . . . . . . . . . . . . . . 149
11.9.2 Start Master Transmit function . . . . . . . . . . . 149
11.9.3 Start Master Receive function . . . . . . . . . . . 149
11.9.4 I
2
C interrupt routine . . . . . . . . . . . . . . . . . . . 150
11.9.5 Non mode specific states. . . . . . . . . . . . . . . 150
11.9.5.1 State: 0x00. . . . . . . . . . . . . . . . . . . . . . . . . . 150
11.9.5.2 Master States. . . . . . . . . . . . . . . . . . . . . . . . 150
11.9.5.3 State: 0x08. . . . . . . . . . . . . . . . . . . . . . . . . . 150
11.9.5.4 State: 0x10. . . . . . . . . . . . . . . . . . . . . . . . . . 150
11.9.6 Master Transmitter states. . . . . . . . . . . . . . . 151
11.9.6.1 State: 0x18. . . . . . . . . . . . . . . . . . . . . . . . . . 151
11.9.6.2 State: 0x20. . . . . . . . . . . . . . . . . . . . . . . . . . 151
11.9.6.3 State: 0x28. . . . . . . . . . . . . . . . . . . . . . . . . . 151
11.9.6.4 State: 0x30. . . . . . . . . . . . . . . . . . . . . . . . . . 151
11.9.6.5 State: 0x38. . . . . . . . . . . . . . . . . . . . . . . . . . 152
11.9.7 Master Receive states . . . . . . . . . . . . . . . . . 152
11.9.7.1 State: 0x40. . . . . . . . . . . . . . . . . . . . . . . . . . 152
11.9.7.2 State: 0x48. . . . . . . . . . . . . . . . . . . . . . . . . . 152
11.9.7.3 State: 0x50. . . . . . . . . . . . . . . . . . . . . . . . . . 152
11.9.7.4 State: 0x58. . . . . . . . . . . . . . . . . . . . . . . . . . 152
11.9.8 Slave Receiver states . . . . . . . . . . . . . . . . . 153
11.9.8.1 State: 0x60. . . . . . . . . . . . . . . . . . . . . . . . . . 153