Sun Microsystems SPARCstation 20 - Page 45

Chapter 21
CODE EXAMPLE 3-3 Sample Listing of the Full Diagnostic Mode Test
SMCC SPARCstation 10/20 UP/MP POST version xxx (xx/xx/xxxx)
CPU_#0 TI, TMS390Z55(3.x) 1Mb External cache
CPU_#2 TI, TMS390Z55(3.x) 1Mb External cache
CPU_#1 ******* NOT installed *******
CPU_#3 ******* NOT installed *******
<<< CPU_00000000 on MBus Slot_00000000 >>> IS RUNNING (MID =
00000008)
MMU Context Table Reg Test
MMU Context Register Test
MMU TLB Bit Pattern Tests
MMU Flush Tests
D-Cache RAM Write/Read Test
D-Cache PTAG Write/Read Test
D-Cache STAG Write/Read Test
I-Cache RAM Write/Read Test
I-Cache PTAG Write/Read Test
I-Cache STAG Write/Read Test
I-Cache Flush Test
Cache Flashclear Test
MXCC Register Test
MXCC E-Cache Tag RAM Test
MXCC E-Cache Data RAM Test (1 MB E$DATA RAM, MXCC_CSR=00000000)
MXCC Non-Cache Block Zero Test
MXCC Non-Cache Block Copy Test
MXCC Cacheable Block Read Test
MXCC Cacheable Block Write Test
EMC/SMC Control Regs Tests
ECC Multiple UE Test
ECC Multiple CE Test
ECC Multiple CE, UE Test
FPU Register File Test
FPU Misaligned Reg Pair Test
FPU Single-precision Tests
FPU Double-precision Tests
FPU SP Invalid CEXC Test
FPU SP Overflow CEXC Test
FPU SP Underflow CEXC Test