Index
Index-5
debug 7-6
examples
code D-7
data logging with end address 7-29
data logging with word counter 7-28
execution control modes
real-time mode 7-9
stop mode 7-7
F
fast function call 6-95
FC (fetch counter) 4-5
fetch counter (FC) 4-5
FFC XAR7,22bit 6-95
find the maximum 6-149
find the minimum 6-153
flags, interrupt flag register (IFR) 3-7
FLIP AX 6-96
flip order of bits in AX register 6-96
flow chart of recommended migration
steps, figure D-4
flow charts
handling DT-DMA request 7-17
interrupt initiated by the TRAP
instruction 3-18
interrupt operation, maskable
interrupts 3-12
foreground code 7-6
full context save D-8
Full Context Save/Restore, figure F-5
Full Context Save/Restore Comparison, table D-9
G
global space C-14
GREG register D-14
H
hardware reset 3-23
hardware reset interrupt 3-17
header, dimensions, 14-pin 7-3
high-impedance mode 7-5
I
I/O space C-14
IACK #16bit 6-97
IC (instruction counter) 4-5
IDLE 6-98
IDLE status bit (IDLESTAT) 2-35
IDLESTAT C-9
IDLESTAT bit 2-35
IEEE 1149.1 (JTAG) signals 7-3
IER A-2
IFR A-2
illegal-instruction trap 3-17, 3-22
IMACL P,loc32,*XAR7 6-100
improvements over the C2xLP CPU C-2
IMPYAL P,XT,loc32 6-103
IMPYL ACC,XT,loc32 6-105
IMPYL P,XT,loc32 6-106
IMPYSL P,XT,loc32 6-107
IMPYXUL P,XT,loc32 6-109
IN loc16,*(PA) 6-111
INC loc16 6-113
increment by 1 6-113
Indirect Addressing Mode 5-2, 5-10
individually accessible portions of the accumula-
tor 2-7
instrucitons, MAX AX,loc16 (find the maxi-
mum) 6-149
instruction
TBIT 6-359
XB 6-370
instruction counter (IC) 4-5
Instruction Syntax Change, table F-12
instruction-fetch mechanism 4-4
instruction-not-available condition 4-10
instructions
ABORTI (abort interrupt) 7-15
ABS ACC (Absolute Value of
Accumulator) 6-19
ADD (add constant) 6-29
ADD AX (Add value to AX) 6-27
ADDACC (Add value to accumulator) 6-22
ADDB XARn, #7bit 6-33
ADDUACC (add unsigned value to
accumulator) 6-39
ADRK (add to current register) 6-42
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