155
D PW A N D
S1
S2
D
D W O R P
S1
S2
D
D W X O R P
S1
S2
D
FNC
26
FNC
27
FNC
28
1
1
1
2
2
2
M
M
M
3
3
3
○
○
○
○
○
○
○
○
○
○
○
○
X Y M S
D.b R.b
KnX KnY
KnM KnS
T C
D,R
V,Z
UnG
K,H
E
" $"
S1
S2
D
S1 : the source device #1
S2 : the source device #2
D : the operation result
S1 : the source device #1
S2 : the source device #2
D : the operation result
S1 : the source device #1
S2 : the source device #2
D : the operation result
0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1
1 1 1 1 1 1 1 1
1 1 1 1
D0
D1
D2
0 0 0 0
0 0 0 0
1 1 1 1
0 0 0 0 0 0 0 0
D3
WXOR D6 D7 D8
X22
D6
0 0 0 0
1 1 1 1
0 0 0 0
1 1 1 1
D5
1 1 1 1 1 1 1 1
D4
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1
0 0 0 0
0 0 0 0
1 1 1 1
0 0 0 0 0 0 0 0
1 1 1 1
D8
1 1 1 1
D7
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
1 1 1 1
0 0 0 0
WAND D0 D1 D2
X20
S1 S 2
D
WOR D3 D4 D5
X21
S1 S2
D
S1 S2
D
X20＝ON
X21＝ON
X22＝ON
Operand
Devices
Logic Word OR (S1)ˇ(S2) → (D)
Logic Word AND (S1) (S2) → (D)
ˇ
Logic Word Exclusive OR
(S1)ˇ(S2) → (D)
When X20 = “ON”, two 16-bit content data in the (D0) and (D1) execute the logic AND operation and restore the
result in (D2).
The logic AND operation result for each bit is: 0 0 = 0, 0 1 = 0, 1 0 = 0 or 1 1 = 1; any “0” at the parallel bits
will cause a result of “0”.
When X21 = “ON”, two 16-bit content data in the (D3) and (D4) execute the logic OR operation and restore the
result in (D5).
The logic OR operation result for each bit is: 0 ˇ 0 = 0, 0 ˇ 1 = 1, 1 0 = 1 or 1 ˇ 1 = 1; any “1” at the parallel
bits will cause a result of “1” .
When X22 = “ON”, two 16-bit content data in the (D6) and (D7) execute the logic XOR operation and restore the
result in (D8).
ˇ ˇ ˇ ˇ
The logic XOR operation result for each bit is: 0 0 = 0, 0 1 = 1, 0 = 1 or 1 1 = 0; the same statuses at
the parallel bits will cause a result of “1”.
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