2-14 Phaser 3250 Laser Printer Service Manual
Theory of Operation
Asic (SPGPv3)
CPU Core: ARM1020E
■ 32KB instruction cache and 32 KB data cache
Operating Frequency
■ CPU Core: Over 300 MHz
■ System Bus: 100 MHz
SDRAMC
■ 32 Bits only, 100 MHz
■ 5 Banks (up to 128 MB per Bank)
ROMC
■ 4 Banks (up to 16 MB per Bank)
IOC
■ 6 Banks (up to 16 per Bank)
DMAC
■ 4 channels
HPVC
■ Dual/Single Beam
■ LVDS Pad (VDO, HSYNC)
UART
■ 5 channels (1 channel supports DMA operation)
PCI Controller
■ 32 Bits, 33/66 MHz
■ PCI Local Bus specification rev2.2 Compliant
■ Host/Agent Mode (supports 4 devices in Host mode)
NAND Flash Controller
■ 8/16 Bits, H/W EEC Generation
■ Auto Boot Mode (using Internal SRAM, 4 KB)
MAC
■ 10 M/100 Mbps
■ Full IEEE 802.3 compatibility
To Next Page
Loading...
