ZiLOG Z8 User Manual

Z8 Microcontrollers
Serial I/O ZiLOG
9-6 UM001601-0803
9.4 TRANSMITTER OPERATION
The transmitter consists of a transmitter buffer (SIO Register
[F0H]), a parity generator, and associated control logic. The
transmitter block diagram is shown as part of Figure 9-1.
After a hardware reset or after a character has been transmitted,
the transmitter is forced to a marking state (output always High)
until a character is loaded into the transmitter buffer, SIO Regis
-
ter (F0H). The transmitter is loaded by specifying the SIO Reg-
ister as the destination register of any instruction.
T0’s output drives a divide-by-16 counter that in turn generates
a shift clock every 16 counts. This counter is reset when the
transmitter buffer is written by an instruction. This reset syn
-
chronizes the shift clock to the software. The transmitter then
outputs one bit per shift clock, through Port 3 bit 7, until a start
bit, the character written to the buffer, and two stop bits have
been transmitted. After the second stop bit has been transmitted,
the output is again forced to a marking state. Interrupt request
IRQ4 is generated at this time to notify the processor that the
transmitter is ready to accept another character.
9.4.1 Overwrites
The user is not protected from overwriting the transmitter, so it
is up to the software to respond to IRQ4 appropriately. If polling
is used, the IRQ4 bit in the Interrupt Request Register must be
reset.
9.4.2 Parity
The data format supported by the transmitter has a start bit, eight
data bits, and at least two stop bits. If parity is on, bit 7 of the data
transmitted will be replaced by an odd parity bit. Figure 9-9
shows the transmitter data formats.
Parity is enabled by setting Port 3 Mode Register bit 7 to 1. If
even parity is required, the parity mode should be disabled (P3M
bit 7 reset to 0), and software must modify the data to include
even parity.
Since the transmitter can be overwritten, the user is able to gen-
erate a break signal. This is done by writing null characters to the
transmitter buffer (SIO Register [F0H]) at a rate that does not al
-
low the stop bits to be output. Each time the SIO Register is load-
ed, the divide-by-16 counter is resynchronized and a new start
bit is output followed by data.
Figure 9-9. Transmitter Data Formats
SP SP D7 D6 D5 D4 D3 D2 D1 D0 ST
Eight Data Bits
Start Bit
Start Bit
Seven Data Bits
Two Stop Bit
SP SP P D6 D5 D4 D3 D2 D1 D0 ST
Odd Parity
Two Stop Bit
Transmitted Data
(No Parity)
Transmitted Data
(With Parity)

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English

Summary

Z8 MCU Product Overview

Z8 MCU Family Overview

Overview of the Z8 MCU product line, its applications, and packaging options.

Key Product Line Features

Details the core features of the Z8 MCU family, including registers, I/O, timers, and interrupts.

Z8 Address Space

Introduction to Address Spaces

Outlines the available address spaces for the Z8 MCU: register, program, and data memory.

Z8 MCU Standard Register File

Describes the structure, layout, and register map of the Z8 standard register file.

Z8 Expanded Register File (ERF)

Details the expansion of the register file into banks for additional features and peripherals.

Z8 Control and Peripheral Registers

Explains the standard and expanded registers governing CPU control and on-chip peripherals.

Program Memory Organization

Covers the reserved areas and organization of program memory, including interrupt vectors.

Z8 External Memory Interface

Describes the interface for accessing external program and data memory.

Z8 Stack Operations

Explains stack operations, location selection, and stack pointer management.

Z8 Clock System

Clock Circuitry and Frequency Control

Details the Z8 MCU's clock circuitry, sources, and frequency control mechanisms.

Clock Control and Modes

Explains software control of the internal system clock and divide-by-16 prescaler.

Oscillator Control and Operation

Covers software control of the oscillator for EMI and operation, including layout rules.

Oscillator Types: LC and RC

Explains the use of LC networks and RC oscillators for XTAL clock generation.

Z8 Reset and Watch-Dog Timer

Z8 MCU Reset Conditions

Covers Z8 MCU reset conditions, timing, and initialization procedures.

Reset Pin and Internal POR Operation

Details the hardware RESET pin and internal Power-On Reset operation.

Watch-Dog Timer (WDT) Functionality

Explains the WDT as a fail-safe mechanism for MCU resets.

Power-On Reset (POR) Circuit

Describes the timer circuit used for the Power-On Reset (POR) function.

Z8 I/O Ports and Configurations

Overview of Z8 I/O Ports

Overview of the Z8's I/O lines, grouping into ports, and general capabilities.

Port 0 Operation and Modes

Details the I/O operation of Port 0, including general I/O and handshake modes.

Port 1 Operation and Modes

Describes the I/O operation of Port 1, including general I/O and handshake modes.

Port 2 Operation and Modes

Explains the general I/O operation of Port 2 and its configurations.

Port 3 Functionality and Modes

Covers the unique structure and I/O capabilities of Port 3, including special functions.

Port Handshake Operation

Details how Ports 0, 1, and 2 use Port 3 for asynchronous data transfer handshake.

I/O Port Reset Conditions

Describes port register states and behavior after hardware, WDT, or POR resets.

Analog Comparators on Port 3

Explains the two on-chip analog comparators and their programming.

Open-Drain, Low EMI, and Auto Latches

Covers open-drain configuration, Low EMI mode, and auto latches for I/O protection.

Z8 Counter/Timers

Counter/Timer Introduction and Registers

Introduces the Z8 MCU's counter/timers, prescalers, and associated registers.

Counter/Timer Operation Modes

Explains how counter/timers are started, stopped, and controlled via Timer Mode Register.

Prescaler Operations and Modes

Details prescaler operations, count modes, and calculating time intervals.

Timer Output (TOUT) and Input (TIN) Modes

Describes TOUT modes for outputting timer states and TIN modes for external clocking.

Cascading Counter/Timers and Reset

Explains cascading counters for longer intervals and reset conditions.

Z8 Interrupt Handling

Interrupt Sources and Control Registers

Lists and describes interrupt sources and control registers (IRQ, IMR, IPR).

Interrupt Request Register Logic

Explains the logic and timing of the Interrupt Request (IRQ) register.

Interrupt Initialization Procedures

Covers the process of initializing interrupt priority, mask, and request registers.

Vectored and Polled Interrupt Processing

Explains vectored interrupt sequences and polled interrupt handling methods.

Z8 Power-Down Modes

HALT Mode Operation

Describes the HALT mode for reducing power consumption by suspending CPU clock.

STOP Mode Operation

Explains the STOP mode for lowest standby current by turning off clocks.

STOP-Mode Recovery Register (SMR)

Details the SMR register for configuring STOP-Mode Recovery sources and delays.

Z8 Serial I/O Interfaces

UART Introduction and Bit-Rate Generation

Introduces the UART for serial data and explains bit-rate generation.

UART Receiver Operation

Covers the UART receiver functionality, including shift register and data formats.

UART Transmitter Operation

Details the UART transmitter functionality, including parity and data formats.

UART Reset Conditions

Describes UART register states and behavior after reset.

Serial Peripheral Interface (SPI)

Introduces the SPI interface, pin configuration, and registers.

SPI Receive Status and Overrun

Explains SPI receive character available status and overrun conditions.

Z8 External Memory Interface

Introduction to External Interface

Overview of Z8 external memory interfacing capabilities and pins.

External Interface Pin Descriptions

Briefly describes pins associated with the Z8 MCU external memory interface.

External Addressing Configuration

Details how to configure ports for external addressing and memory mapping.

External Stacks and Data Memory

Explains Z8 stack operations in external memory and data memory addressing.

Bus Operation and Timing

Illustrates typical data transfers on the external bus and extended bus timing.

Instruction Timing

Shows typical instruction cycle timing for memory-fetched instructions.

Z8 Addressing Modes

Introduction to Addressing Modes

Introduces the six addressing modes provided by the Z8 microcontroller.

Register Addressing (R)

Explains 8-bit and 4-bit register addressing modes.

Indirect Register Addressing (IR)

Details indirect register addressing for accessing operands via registers.

Indexed Addressing (X)

Explains indexed addressing using a register offset for address calculation.

Direct Addressing (DA)

Describes direct addressing for specifying the next instruction address.

Relative Addressing (RA)

Covers relative addressing for jumps based on PC displacement.

Immediate Data Addressing (IM)

Explains immediate addressing where the operand is part of the instruction.

Z8 Instruction Set Details

Z8 Functional Summary of Instructions

Lists Z8 instructions grouped by function: Load, Arithmetic, Logical, etc.

Processor Flags and Status

Describes the Z8's status flags (Carry, Zero, Sign, Overflow, etc.) and their meanings.

Condition Codes for Jumps

Summarizes flag settings used for conditional jump instructions.

Instruction Notation and Binary Encoding

Explains the shorthand notation for operands, modes, and binary encoding.

Z8 Instruction Summary and Op Codes

Provides a summary of Z8 instructions with opcodes, cycles, and address modes.

Detailed Instruction Descriptions

Details the format, operation, flags, and examples for individual Z8 instructions.