UM001601-0803 5-1
USER’S MANUAL
CHAPTER 5
I/O PORTS
5.1 I/O PORTS
The Z8 has up to 32 lines dedicated to input and output. These
lines are grouped into four 8-bit ports known as Port 0, Port 1,
Port 2, and Port 3. Port 0 is nibble programmable as input, out
-
put, or address. Port 1 is byte configurable as input, output, or ad-
dress/data. Port 2 is bit programmable as either inputs or outputs,
with or without handshake and SPI. Port 3 can be programmed
to provide timing, serial and parallel input/output, or comparator
input/output.
All ports have push-pull CMOS outputs. In addition, the push-
pull outputs of Port 2 can be turned off for open-drain operation.
5.1.1 Mode Registers
Each port has an associated Mode Register that determines the
port’s functions and allows dynamic change in port functions
during program execution. Port and Mode Registers are mapped
into the Standard Register File as shown in Figure 5-1.
Because of their close association, Port and Mode Registers are
treated like any other general-purpose register. There are no spe
-
cial instructions for port manipulation. Any instruction which
addresses a register can address the ports. Data can be directly
accessed in the Port Register, with no extra moves.
5.1.2 Input and Output Registers
Each bit of Ports 0, 1, and 2, have an input register, an output reg-
ister, associated buffer, and control logic. Since there are sepa-
rate input and output registers associated with each port, writing
to bits defined as inputs stores the data in the output register. This
data cannot be read as long as the bits are defined as inputs. How
-
ever, if the bits are reconfigured as outputs, the data stored in the
output register is reflected on the output pins and can then be
read. This mechanism allows the user to initialize the outputs pri
-
or to driving their loads (Figure 5-2).
Since port inputs are asynchronous to the Z8 internal clock, a
READ operation could occur during an input transition. In this
case, the logic level might be uncertain (somewhere between a
logic 1 and 0). To eliminate this meta-stable condition, the Z8
latches the input data two clock periods prior to the execution of
the current instruction. The input register uses these two clock
periods to stabilize to a legitimate logic level before the instruc
-
tion reads the data.
Note: The following sections describe the generic function of
the Z8 ports. Any additional features of the ports such as SPI,
C/T, and Stop-Mode Recovery are covered in their own section.
Figure 5-1. I/O Ports and Mode Registers
Register
HEX
Port 3 Mode
Port 2 Mode
Identifier
F8H
F7H
F6H
P01M
P3M
P2M
Port 3
Port 0-1 Mode
Port 2
Port 1
Port 0
03H
02H
01H
00H
P3
P2
P1
P0
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