ZiLOG Z8

Z8 Microcontrollers
I/O Ports ZiLOG
5-2 UM001601-0803
5.2 PORT 0
This section deals with only the I/O operation of Port 0. The
port's external memory interface operation is covered later in
this manual. Figure 5-2 shows a block diagram of Port 0. This di-
agram also applies to Ports 1 and 2.
Figure 5-2. Ports 0, 1, 2 Generic Block Diagram
Handshake
Logic
Internal
Timing
Handshake
Selected
RDY//DAV
/DAV/RDY
Port I/O
Lines
Input
Buffer
Input
Register
Handshake
Logic
Output
Buffer
Output
Register
Output
Enable
Internal
Bus
Write
Port
Read
Port
E
88
8
88
8
8