Z8 Microcontrollers
ZiLOG Counter/Timers
UM001601-0803 6-9
6.5.2 Gated Internal Clock Mode
The T
IN
Gated Internal Clock Mode (TMR bit 5 and bit 4 set to
0 and 1 respectively) measures the duration of an external event.
In this mode, the T1 prescaler is driven by the internal timer
clock, gated by a High level on T
IN
(Figure 6-16). T1 counts
while T
IN
is High and stops counting while
T
IN
is Low. Interrupt request IRQ2 is generated on the High-to-
Low transition of T
IN
signalling the end of the gate input. Inter-
rupt request IRQ5 is generated if T1 reaches its end-of-count.
Figure 6-16. Gated Clock Input Mode
OSC
÷2
÷4
D D
PRE1
P3
1
T1
IRQ
2
T
IN
IRQ
5
Gate
Internal
TMR
D
5 -
D
4
= 01
Clock
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