Z8 Microcontrollers
Instruction Set ZiLOG
12-2 UM001601-0803
12.2 PROCESSOR FLAGS
The Flag Register (FCH) informs the user of the current status of
the Z8. The flags and their bit positions in the Flag Register are
shown in Figure 12-1.
The Z8 Flag Register contains six bits of status information
which are set or cleared by CPU operations. Four of the bits (C,
V, Z and S) can be tested for use with conditional Jump instruc
-
tions. Two flags (H and D) cannot be tested and are used for
BCD arithmetic. The two remaining bits in the Flag Register (F1
and F2) are available to the user, but they must be set or cleared
by instructions and are not usable with conditional Jumps.
As with bits in the other control registers, the Flag Register bits
can be set or reset by instructions; however, only those instruc
-
tions that do not affect the flags as an outcome of the execution
should be used (Load Immediate).
Note: The Watch-Dog Timer (WDT) instruction effects the
Flags accordingly: Z=1, S=0, V=0.
Tab le 12-5. Bit Manipulation Instructions
Mnemonic Operands Instruction
TCM dst, src Test Complement
Under Mask
TM dst, src Test Under Mask
AND dst, src Bit Clear
OR dst, src Bit Set
XOR dst, src Bit Complement
Table 12-6. Block Transfer Instructions
Mnemonic Operands Instruction
LDCI dst, src Load Constant
Auto Increment
LDEI dst, src Load External
Auto Increment
Table 12-7. Rotate and Shift Instructions
Mnemonic Operands Instruction
RL dst Rotate Left
RLC dst Rotate Left Through Carry
RR dst Rotate Right
RRC dst Rotate Right Through Carry
SRA dst Shift Right Arithmetic
SWAP dst Swap Nibbles
Table 12-8. CPU Control Instructions
Mnemonic Operands Instruction
CCF Complement Carry Flag
DI Disable Interrupts
EI Enable Interrupts
HALT Halt
NOP No Operation
RCF Reset Carry Flag
SCF Set Carry Flag
SRP src Set Register Pointer
STOP Stop
WDH WDT Enable During HALT
WDT WDT Enable or Refresh
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