Z8 Microcontrollers
ZiLOG Serial I/O
UM001601-0803 9-9
9.7 SPI OPERATION
The SPI is used in one of two modes: either as system slave, or
as system master. Several of the possible system configurations
are shown in Figure 9-13. In the slave mode, data transfer starts
when the slave select (SS) pin goes active. Data is transferred
into the slave’s SPI Shift Register through the DI pin, which has
the same address as the RxBUF Register. After a byte of data has
been received by the SPI Shift Register, a Receive Character
Available (RCA/IRQ3) flag and interrupt is generated. The next
byte of data will be received at this time. The RxBUF Register
must be cleared, or a Receive Character Overrun (RxCharOver
-
run) flag will be set in the SCON Register, and the data in the
RxBUF Register will be overwritten. When the communication
between the master and slave is complete, the SS goes inac
-
tive.When the SPI is activated as a slave, it operates in all system
modes: STOP, HALT, and RUN.
Unless disconnected, for every bit that is transferred into the
slave through the DI pin, a bit is transferred out through the D0
pin on the opposite clock edge. During slave operation, the SPI
clock pin (SK) is an input. In master mode, the CPU must first
activate a SS through one of its I/O ports. Next, data is trans
-
ferred through the master’s D0 pin one bit per master clock cy-
cle. Loading data into the shift register initiates the transfer. In
master mode, the master’s clock will drive the slave’s clock. At
the conclusion of a transfer, a Receive Character Available
(RCA/IRQ3) flag and interrupt is generated. Before data is trans
-
ferred via the D0 pin, the SPI Enable bit in the SCON Register
must be enabled.
9.8 SPI COMPARE
When the SPI Compare Enable bit, D3 of the SCON Register is
set to 1, the SPI Compare feature is enabled. The compare fea
-
ture is only valid for slave mode. A compare transaction begins
when the (SS) line goes active. Data is received as if it were a
normal transaction, but there is no data transmitted to avoid bus
contention with other slave devices. When the compare byte is
received, IRQ3 is not generated. Instead, the data is compared
with the contents of the SCOMP Register. If the data does not
match, DO remains inactive and the slave ignores all data until
the (SS) signal is reset. If the data received matches the data in
the SCOMP register, then a SMR signal is generated. DO is ac
-
tivated if it is not tri-stated by D2 in the SCON Register, and data
is received the same as any other SPI slave transaction.
Slaves’ not comparing remain in their current mode, whereas
slaves’ comparing wake from a STOP mode by means of an
SMR
9.9 SPI CLOCK
The SPI clock maybe driven by three sources: Timer0, a division
of the internal system clock, or the external master when in slave
mode. Bit D6 of the SCON Register controls what source drives
the SPI clock. A 0 in bit D6 of the SCON Register determines
the division of the internal system clock if this is used as the SPI
clock source. Divide by 2, 4, 8, or 16 is chosen as the scaler.
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