Z8 Microcontrollers
ZiLOG Interrupts
UM001601-0803 7-9
7.5 IRQ SOFTWARE INTERRUPT GENERATION
IRQ can be used to generate software interrupts by specifying
IRQ as the destination of any instruction referencing the Z8
Standard Register File. These Software Interrupts (SWI) are
controlled in the same manner as hardware generated requests
(in other words, the IPR and the IMR control the priority and en
-
abling of each SWI level).
To generate a SWI, the desired request bit in the IRQ is set as fol-
lows:
where the immediate data, NUMBER, has a 1 in the bit position
corresponding to the level of the SWI desired. For example, if an
SWI is desired on IRQ5, NUMBER would have a 1 in bit 5:
With this instruction, if the interrupt system is globally enabled,
IRQ5 is enabled, and there are no higher priority pending re
-
quests, control is transferred to the service routine pointed to by
the IRQ5 vector.
7.6 VECTORED PROCESSING
Each Z8 interrupt level has its own vector. When an interrupt oc-
curs, control passes to the service routine pointed to by the inter-
rupt’s vector location in program memory. The sequence of
events for vectored interrupts is as follows:
• PUSH PC Low Byte on Stack
• PUSH PC High Byte on Stack
• PUSH FLAGS on Stack
• Fetch High Byte of Vector
• Fetch Low Byte of Vector
• Branch to Service Routine specified by Vector
Figures 7-11 and 7-12 show the vectored interrupt operation.
ORIRQ, #NUMBER
OR IRQ, #00100000B
Figure 7-11. Effects of an Interrupt on the STACK
SP
Top of Stack
PC LOW Byte
PC HIGH Byte
FLAGS
SP and Stack after an interrupt
SP
SP and Stack before an interrupt
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