Z8 Microcontrollers
External Interface ZiLOG
10-2 UM001601-0803
10.2 PIN DESCRIPTIONS
The following sections briefly describe the pins associated with
the Z8 MCU
®
external memory interface.
10.2.1 /AS
Address Strobe (output, active Low). Address Strobe is pulsed
Low once at the beginning of each machine cycle. The rising
edge of
AS indicates the address, Read/Write (R/W), and Data
Memory (
DM) signals are valid for program or data memory
transfers. In some cases, the Z8 address strobe is pulsed low re
-
gardless of accessing external or internal memory. Please refer
to specific product specifications for
AS operation.
10.2.2 DS
Data Strobe (Output, Active Low). Data Strobe provides the
timing for data movement to or from the Address/Data bus for
each external memory transfer. During a Write Cycle, data out is
valid at the leading edge of the
DS. During a Read Cycle, data in
must be valid prior to the trailing edge of the
DS.
10.2.3 R/W
Read/Write (Output). Read/Write determines the direction of
data transfer for memory transactions. R/
W is Low when writing
to program or data memory, and High for all other transactions.
10.2.4 DM
Data Memory (Output). Data Memory provides a signal to sep-
arate External Program Memory from External Data Memory. It
is a programmable function on pin P34. Data memory is active
low for External Data Memory accesses and high for External
Program Memory accesses.
10.2.5 P07 - P00
High Address Lines A15 -A8 (Outputs can be CMOS- or TTL-
compatible. Please refer to product specifications for actual
type). A15-A8 provide the High Address lines for the memory
interface. Port 0 - 1 mode register must have bits D7 = 1 and D1
= 1 to configure Port 0 as A15 - A8 (Figure 10-2).
10.2.6 P17 - P10
Address/Data Lines AD7 - AD0 (inputs/outputs, TTL-compati-
ble). AD7-AD0 is a multiplexed Address/Data memory inter-
face. The lower eight Address lines (A7-A0) are multiplexed
with Data lines (D7-D0). Port 0 - 1 mode register must have bits
D4 = 1 and D3 = 0 to configure Port 1 as AD7 - AD0 (Figure 10-
2).
10.2.7 /RESET
Reset (input, active Low). RESET initializes the Z8. When
RESET is deactivated, program execution begins from program
location 000CH. If held Low,
RESET acts as a register file
protect during power-down and power-up sequences. To avoid
asynchronous and noisy reset problems, the Z8 is equipped with
a reset filter of four external clocks (4T
P
C). If the external
RESET signal is less than 4T
P
C in duration, no reset will occur.
On the fifth clock after the
RESET is detected, an internal reset
signal is latched and held for an internal register count of 18 or
more external clocks, or for the duration of the external
RESET,
whichever is longer. Please refer to specific product
specifications for length of reset delay time.
10.2.8 XTAL1, XTAL2.
Crystal1, Crystal2 (Oscillator input and output). These pins con-
nect a parallel-resonant crystal, ceramic resonator, LC, RC net-
work, or external single-phase clock to the on-chip oscillator in-
put. Please refer to the device product specifications for
information on availability of RC oscillator features.
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