Z8 Microcontrollers
ZiLOG Reset—Watch-Dog Timer
UM001601-0803 4-7
4.3 WATCH-DOG TIMER (WDT)
The WDT is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. When operating in the RUN or HALT
modes, a WDT reset is functionally equivalent to a hardware
POR reset. The WDT is initially enabled by executing the WDT
instruction and refreshed on subsequent executions of the WDT
instruction. The WDT cannot be disabled after it has been initial
-
ly enabled. Permanently enabled WDTs are always enabled and
the WDT instruction is used to refresh it. The WDT circuit is
driven by an on-board RC oscillator or external oscillator from
the XTAL1 pin. The POR clock source is selected with bit 4 of
the Watch-Dog Timer Mode register (WDTMR). In some cases,
a Z8 that offers the WDT but does not have a WDTMR register,
has a fixed WDT timeout and uses the on board RC oscillator as
the only clock source. Please refer to specific product specifica
-
tions for selectability of timeout, WDT during HALT and STOP
modes, source of WDT clock, and availability of the permanent
-
ly-on WDT option.
Note: Execution of the WDT instruction affects the Z (zero), S
(sign), and V (overflow) flags.
Note: The WDTMR register is accessible only during the first
60 processor cycles from the execution of the first instruction
after Power-On Reset, Watch-Dog Reset or a Stop-Mode
Recovery. After this point, the register cannot be modified by
any means, intentional or otherwise. The WDTMR is a write-
only register.
The WDTMR is located in Expanded Register File Bank F, reg-
ister 0FH. The control bits are described as follows:
WDT Time Select (D1, D0). Bits 0 and 1 control a tap circuit
that determines the time-out period. Table 4-5 shows the differ
-
ent values that can be obtained. The default value of D1 and D0
are 0 and 1, respectively.
WDT During HALT (D2). This bit determines whether or not
the WDT is active during HALT mode. A 1 indicates active dur
-
ing HALT. The default is 1. A WDT time out during HALT
mode will reset control register ports to their default reset condi
-
tions.
WDT During STOP (D3). This bit determines whether or not
the WDT is active during STOP mode. Since XTAL clock is
stopped during STOP Mode, unless as specified below, the on-
board RC must be selected as the clock source to the POR
counter. A 1 indicates active during STOP. The default is 1. If
bits D3 and D4 are both set to 1, the WDT only, is driven by the
external clock during STOP mode. This feature makes it possi
-
ble to wake up from STOP mode from an internal source. Please
refer to specific product specifications for conditions of control
and port registers when the Z8 comes out of STOP mode. A
WDT time out during STOP mode will not reset all control reg
-
isters. The reset conditions of the ports from STOP mode due to
WDT time out is the same as if recovered using any of the other
STOP mode sources.
Figure 4-5. Example of Z8 Watch-Dog Timer Mode
Register (Write-Only)
D7 D6 D5 D4 D3 D2 D1 D0
WDTMR (F) 0F
INT
00 5 128
01** 10 256
10 20 512
11 80 2048
WDT RC SYS
TAP* OSC CLK
WDT During STOP
0 OFF
1 ON *
WDT During HALT
0 OFF
1 ON *
XTAL1/INT RC
0 On-Board RC *
1 XTAL
Reserved (Must be 0)
Select for WDT
* Must be 0 for Z86C03
Reserved (Must be 0)
** Default setting after RESET
Table 4-5. Time-Out Period of the WDT
Typical
Time-Out of Time-Out of
D1 D0 Internal RC OSC SYS Clock
0 0 5 ms min 256TpC
0 1 15 ms min 512TpC
1 0 25 ms min 1024TpC
1 1 100 ms min 4096TpC
Notes:
TpC = XTAL clock cycle
The default on reset is, D0 = 1 and D1 = 0.
The values given are for VCC = 5.0V.
See the device product specification for exact WDTMR time
out select options available.
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