ZiLOG Z8 User Manual

Z8 Microcontrollers
Address Space ZiLOG
2-12 UM001601-0803
2.7 Z8 STACKS
Stack operations can occur in either the Z8 MCU Standard Reg-
ister File or external data memory. Under software control, Port
0–1 Mode register (F8H) selects the stack location. Only the
General-Purpose Registers can be used for the stack when the in
-
ternal stack is selected.
The register pair FEH and FFH form the 16-bit Stack Pointer
(SP), that is used for all stack operations. The stack address is
stored with the MSB in FEH and LSB in FFH (Figure 2-9).
The stack address is decremented prior to a PUSH operation and
incremented after a POP operation. The stack address always
points to the data stored on the top of the stack. The Z8 stack is
a return stack for CALL instructions and interrupts, as well as a
data stack.
During a CALL instruction, the contents of the PC are saved on
the stack. The PC is restored during a RETURN instruction. In
-
terrupts cause the contents of the PC and Flag registers to be
saved on the stack. The IRET instruction restores them (Figure
2-10).
When the Z8 is configured for an internal stack (using the Z8
Standard Register File), register FFH serves as the Stack Pointer.
The value in FEH is ignored. FEH can be used as a general-pur
-
pose register in this case only.
An overflow or underflow can occur when the stack address is
incremented or decremented during normal stack operations.
The programmer must prevent this occurrence or unpredictable
operation will result.
Figure 2-9. Stack Pointer
UPPER Byte
LOWER Byte
Stack Pointer High
FFH
Stack Pointer Low
FEH
Figure 2-10. Stack Operations
PCL
Top of Stack
Stack Contents
PCH
PCL
PCH
FLAGS
After an
Interrupt Cycle
Stack Contents
After a Call
Instruction
Top of Stack

ZiLOG Z8 Specifications

General

Brand	ZiLOG
Model	Z8
Category	Desktop
Language	English

Summary

Z8 MCU Product Overview

Z8 MCU Family Overview

Overview of the Z8 MCU product line, its applications, and packaging options.

Key Product Line Features

Details the core features of the Z8 MCU family, including registers, I/O, timers, and interrupts.

Z8 Address Space

Introduction to Address Spaces

Outlines the available address spaces for the Z8 MCU: register, program, and data memory.

Z8 MCU Standard Register File

Describes the structure, layout, and register map of the Z8 standard register file.

Z8 Expanded Register File (ERF)

Details the expansion of the register file into banks for additional features and peripherals.

Z8 Control and Peripheral Registers

Explains the standard and expanded registers governing CPU control and on-chip peripherals.

Program Memory Organization

Covers the reserved areas and organization of program memory, including interrupt vectors.

Z8 External Memory Interface

Describes the interface for accessing external program and data memory.

Z8 Stack Operations

Explains stack operations, location selection, and stack pointer management.

Z8 Clock System

Clock Circuitry and Frequency Control

Details the Z8 MCU's clock circuitry, sources, and frequency control mechanisms.

Clock Control and Modes

Explains software control of the internal system clock and divide-by-16 prescaler.

Oscillator Control and Operation

Covers software control of the oscillator for EMI and operation, including layout rules.

Oscillator Types: LC and RC

Explains the use of LC networks and RC oscillators for XTAL clock generation.

Z8 Reset and Watch-Dog Timer

Z8 MCU Reset Conditions

Covers Z8 MCU reset conditions, timing, and initialization procedures.

Reset Pin and Internal POR Operation

Details the hardware RESET pin and internal Power-On Reset operation.

Watch-Dog Timer (WDT) Functionality

Explains the WDT as a fail-safe mechanism for MCU resets.

Power-On Reset (POR) Circuit

Describes the timer circuit used for the Power-On Reset (POR) function.

Z8 I/O Ports and Configurations

Overview of Z8 I/O Ports

Overview of the Z8's I/O lines, grouping into ports, and general capabilities.

Port 0 Operation and Modes

Details the I/O operation of Port 0, including general I/O and handshake modes.

Port 1 Operation and Modes

Describes the I/O operation of Port 1, including general I/O and handshake modes.

Port 2 Operation and Modes

Explains the general I/O operation of Port 2 and its configurations.

Port 3 Functionality and Modes

Covers the unique structure and I/O capabilities of Port 3, including special functions.

Port Handshake Operation

Details how Ports 0, 1, and 2 use Port 3 for asynchronous data transfer handshake.

I/O Port Reset Conditions

Describes port register states and behavior after hardware, WDT, or POR resets.

Analog Comparators on Port 3

Explains the two on-chip analog comparators and their programming.

Open-Drain, Low EMI, and Auto Latches

Covers open-drain configuration, Low EMI mode, and auto latches for I/O protection.

Z8 Counter/Timers

Counter/Timer Introduction and Registers

Introduces the Z8 MCU's counter/timers, prescalers, and associated registers.

Counter/Timer Operation Modes

Explains how counter/timers are started, stopped, and controlled via Timer Mode Register.

Prescaler Operations and Modes

Details prescaler operations, count modes, and calculating time intervals.

Timer Output (TOUT) and Input (TIN) Modes

Describes TOUT modes for outputting timer states and TIN modes for external clocking.

Cascading Counter/Timers and Reset

Explains cascading counters for longer intervals and reset conditions.

Z8 Interrupt Handling

Interrupt Sources and Control Registers

Lists and describes interrupt sources and control registers (IRQ, IMR, IPR).

Interrupt Request Register Logic

Explains the logic and timing of the Interrupt Request (IRQ) register.

Interrupt Initialization Procedures

Covers the process of initializing interrupt priority, mask, and request registers.

Vectored and Polled Interrupt Processing

Explains vectored interrupt sequences and polled interrupt handling methods.

Z8 Power-Down Modes

HALT Mode Operation

Describes the HALT mode for reducing power consumption by suspending CPU clock.

STOP Mode Operation

Explains the STOP mode for lowest standby current by turning off clocks.

STOP-Mode Recovery Register (SMR)

Details the SMR register for configuring STOP-Mode Recovery sources and delays.

Z8 Serial I/O Interfaces

UART Introduction and Bit-Rate Generation

Introduces the UART for serial data and explains bit-rate generation.

UART Receiver Operation

Covers the UART receiver functionality, including shift register and data formats.

UART Transmitter Operation

Details the UART transmitter functionality, including parity and data formats.

UART Reset Conditions

Describes UART register states and behavior after reset.

Serial Peripheral Interface (SPI)

Introduces the SPI interface, pin configuration, and registers.

SPI Receive Status and Overrun

Explains SPI receive character available status and overrun conditions.

Z8 External Memory Interface

Introduction to External Interface

Overview of Z8 external memory interfacing capabilities and pins.

External Interface Pin Descriptions

Briefly describes pins associated with the Z8 MCU external memory interface.

External Addressing Configuration

Details how to configure ports for external addressing and memory mapping.

External Stacks and Data Memory

Explains Z8 stack operations in external memory and data memory addressing.

Bus Operation and Timing

Illustrates typical data transfers on the external bus and extended bus timing.

Instruction Timing

Shows typical instruction cycle timing for memory-fetched instructions.

Z8 Addressing Modes

Introduction to Addressing Modes

Introduces the six addressing modes provided by the Z8 microcontroller.

Register Addressing (R)

Explains 8-bit and 4-bit register addressing modes.

Indirect Register Addressing (IR)

Details indirect register addressing for accessing operands via registers.

Indexed Addressing (X)

Explains indexed addressing using a register offset for address calculation.

Direct Addressing (DA)

Describes direct addressing for specifying the next instruction address.

Relative Addressing (RA)

Covers relative addressing for jumps based on PC displacement.

Immediate Data Addressing (IM)

Explains immediate addressing where the operand is part of the instruction.

Z8 Instruction Set Details

Z8 Functional Summary of Instructions

Lists Z8 instructions grouped by function: Load, Arithmetic, Logical, etc.

Processor Flags and Status

Describes the Z8's status flags (Carry, Zero, Sign, Overflow, etc.) and their meanings.

Condition Codes for Jumps

Summarizes flag settings used for conditional jump instructions.

Instruction Notation and Binary Encoding

Explains the shorthand notation for operands, modes, and binary encoding.

Z8 Instruction Summary and Op Codes

Provides a summary of Z8 instructions with opcodes, cycles, and address modes.

Detailed Instruction Descriptions

Details the format, operation, flags, and examples for individual Z8 instructions.