Allwinner A20 - Page 107

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 107 / 812
1.8.3.3. PWM CHANNEL 1 PERIOD REGISTER
Offset: 0x208
Register Name: PWM_CH1_PERIOD
Bit
Read/
Write
Default/Hex
Description
31:16
R/W
x
PWM_CH1_ENTIRE_CYS
Number of the entire cycles in the PWM clock.
0 = 1 cycle
1 = 2 cycles
……
N = N+1
If the register needs to be modified dynamically, the PCLK
should be faster than the PWM CLK(PWM CLK =
24MHz/prescale).
15:0
R/W
x
PWM_CH1_ENTIRE_CYS
Number of the active cycles in the PWM clock.
0 = 0 cycle
1 = 1 cycles
……
N = N cycles