Allwinner A20 - Page 106

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 106 / 812
Offset: 0x200
Register Name: PWM_CTRL_REG
Bit
Read/
Write
Default/Hex
Description
0100: /480
0101: /
0110: /
0111: /
1000: /12k
1001: /24k
1010: /36k
1011: /48k
1100: /72k
1101: /
1110: /
1111: /1
1.8.3.2. PWM CHANNEL 0 PERIOD REGISTER
Offset: 0x204
Register Name: PWM_CH0_PERIOD
Bit
Read/
Write
Default/Hex
Description
31:16
R/W
x
PWM_CH0_ENTIRE_CYS
Number of the entire cycles in the PWM clock.
0 = 1 cycle
1 = 2 cycles
……
N = N+1 cycles
If the register needs to be modified dynamically, the PCLK
should be faster than the PWM CLK(PWM CLK =
24MHz/prescale).
15:0
R/W
x
PWM_CH0_ENTIRE_ACT_CYS
Number of the active cycles in the PWM clock.
0 = 0 cycle
1 = 1 cycles
……
N = N cycles
Note: the active cycles should be no larger than the period cycles.