Allwinner A20 - Page 105

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 105 / 812
Offset: 0x200
Register Name: PWM_CTRL_REG
Bit
Read/
Write
Default/Hex
Description
1100: /72k
1101: /
1110: /
1111: /1
14:10
/
/
/
9
R/W
0x0
PWM0_BYPASS.
PWM CH0 bypass enable.
If the bit is set to 1, PWM0’s output is OSC24MHz.
0: disable,
1: enable.
8
R/W
0x0
PWM_CH0_PUL_START.
PWM Channel 0 pulse output start.
0: no effect, 1: output 1 pulse.
The pulse width should be according to the period 0
register[15:0],and the pulse state should be according to the
active state.
After the pulse is finished,the bit will be cleared automatically.
7
R/W
0x0
PWM_CHANNEL0_MODE.
0: cycle mode, 1: pulse mode.
6
R/W
0x0
SCLK_CH0_GATING.
Gating the Special Clock for PWM0(0: mask, 1: pass).
5
R/W
0x0
PWM_CH0_ACT_STA.
PWM Channel 0 Active State.
0: Low Level, 1: High Level.
4
R/W
0x0
PWM_CH0_EN.
PWM Channel 0 Enable.
0: Disable, 1: Enable.
3:0
R/W
0x0
PWM_CH0_PRESCAL.
PWM Channel 0 Prescalar.
These bits should be setting before the PWM Channel 0
clock gate on.
0000: /120
0001: /180
0010: /240
0011: /360