Allwinner A20 - Page 130

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 130 / 812
Offset: 0x110
Register Name: ALARM_WK_HH_MM-SS
Bit
Read/
Write
Default/Hex
Description
7:6
/
/
/.
5:0
R/W
x
SECOND.
Range from 0~59.
1.9.3.31. ALARM ENABLE REGISTER
Offset: 0x114
Register Name: ALARM_EN_REG
Bit
Read/
Write
Default/Hex
Description
31:9
/
/
/.
8
R/W
0x0
ALM_CNT_EN.
Alarm Counter Enable.
If this bit is set to “1”, the Alarm Counter DD-HH-MM-SS
register’s valid bits will down count to zero, and the the
alarm pending bit will be set to “1”.
0:disable,
1:enable.
7
/
/
/
6
R/W
0x0
WK6_ALM_EN.
Week 6(Sunday) Alarm Enable.
0: Disable, 1: Enable.
If this bit is set to “1”, only when the Alarm Week HH-MM-SS
register valid bits is equal to RTC HH-MM-SS register and
the register RTC HH-MM-SS bit[31:29] is 6, the week 6
alarm irq pending bit will be set to “1”.
5
R/W
0x0
WK5_ALM_EN.
Week 5(Saturday) Alarm Enable.
0: Disable, 1: Enable.
If this bit is set to “1”, only when the Alarm Week HH-MM-SS
register valid bits is equal to RTC HH-MM-SS register and
the register RTC HH-MM-SS bit[31:29] is 5, the week 5
alarm irq pending bit will be set to “1”.
4
R/W
0x0
WK4_ALM_EN.
Week 4(Friday) Alarm Enable.
0: Disable, 1: Enable.
If this bit is set to “1”, only when the Alarm Week HH-MM-SS