Allwinner A20 - Page 131

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 131 / 812
Offset: 0x114
Register Name: ALARM_EN_REG
Bit
Read/
Write
Default/Hex
Description
register valid bits is equal to RTC HH-MM-SS register and
the register RTC HH-MM-SS bit[31:29] is 4, the week 4
alarm irq pending bit will be set to “1”.
3
R/W
0x0
WK3_ALM_EN.
Week 3(Thursday) Alarm Enable.
0: Disable, 1: Enable.
If this bit is set to “1”, only when the Alarm Week HH-MM-SS
register valid bits is equal to RTC HH-MM-SS register and
the register RTC HH-MM-SS bit[31:29] is 3, the week 3
alarm irq pending bit will be set to “1”.
2
R/W
0x0
WK2_ALM_EN.
Week 2(Wednesday) Alarm Enable.
0: Disable, 1: Enable.
If this bit is set to “1”, only when the Alarm Week HH-MM-SS
register valid bits is equal to RTC HH-MM-SS register and
the register RTC HH-MM-SS bit[31:29] is 2, the week 2
alarm irq pending bit will be set to “1”.
1
R/W
0x0
WK1_ALM_EN.
Week 1(Tuesday) Alarm Enable.
0: Disable, 1: Enable.
If this bit is set to “1”, only when the Alarm Week HH-MM-SS
register valid bits is equal to RTC HH-MM-SS register and
the register RTC HH-MM-SS bit[31:29] is 1, the week 1
alarm irq pending bit will be set to “1”.
0
R/W
0x0
WK0_ALM_EN.
Week 0(Monday) Alarm Enable.
0: Disable, 1: Enable.
If this bit is set to “1”, only when the Alarm Week HH-MM-SS
register valid bits is equal to RTC HH-MM-SS register and
the register RTC HH-MM-SS bit[31:29] is 0, the week 0
alarm irq pending bit will be set to “1”.
1.9.3.32. ALARM IRQ ENABLE REGISTER
Offset: 0x118
Register Name: ALARM_IRQ_EN
Bit
Read/
Write
Default/Hex
Description
31:2
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