Allwinner A20 - Page 132

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 132 / 812
Offset: 0x118
Register Name: ALARM_IRQ_EN
Bit
Read/
Write
Default/Hex
Description
1
R/W
0x0
ALARM_WK_IRQ_EN.
Alarm Week IRQ Enable.
0:disable, 1:enable.
0
R/W
0x0
ALARM_CNT_IRQ_EN.
Alarm Counter IRQ Enable.
0:disable, 1:enable.
1.9.3.33. ALARM IRQ STATUS REGISTER
Offset: 0x11C
Register Name: ALARM_IRQ_STA_REG
Bit
Read/
Write
Default/Hex
Description
31:2
/
/
/.
1
R/W
0x0
WEEK_IRQ_PEND.
Alarm Week (0/1/2/3/4/5/6) IRQ Pending.
0: No effect, 1: Pending, week counter value is reached.
If alarm week irq enable is set to 1, the pending bit will be
sent to the interrupt controller.
0
R/W
0x0
CNT_IRQ_PEND.
Alarm Counter IRQ Pending bit.
0: No effect, 1: Pending, alarm counter value is reached.
If alarm counter irq enable is set to 1, the pending bit will be
sent to the interrupt controller.
1.9.3.34. TIMER GENERAL PURPOSE REGISTER
Offset: 0x120+N*0x4
(N=0~15)
Register Name: TMR_GP_DATA_REG
Bit
Read/
Write
Default/Hex
Description
31:0
R/W
x
TMR_GP_DATA.
Data[31:0].
Note: Timer general purpose register value can be stored if the RTCVDD is above 1.0V.