Allwinner A20 - Page 140

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 140 / 812
Offset:0x30
Register Name:HS_TMR1_CTRL_REG
Bit
Read/
Write
Default/H
ex
Description
7
R/W
0x0
HS_TMR1_MODE.
High Speed Timer 1 mode.
0: Continuous mode. When interval value reached, the timer will
not disable automatically.
1: Single mode. When interval value reached, the timer will
disable automatically.
6:4
R/W
0x0
HS_TMR1_CLK_SRC.
Select the pre-scale of the high speed timer 1 clock sources.
000: /1
001: /2
010: /4
011: /8
100: /16
101: /
110: /
111: /
3:2
/
/
/
1
R/W
0x0
HS_TMR1_RELOAD.
High Speed Timer 1 Reload.
0: No effect, 1: Reload High Speed Timer 1 Interval Value.
0
R/W
0x0
HS_TMR1_EN.
High Speed Timer 1 Enable.
0: Stop/Pause, 1: Start.
If the timer is started, it will reload the interval value to internal
register, and the current counter will count from interval value to
0.
If the current counter does not reach the zero, the timer enable
bit is set to “0”, the current value counter will pause. At least
wait for 2 cycles, the start bit can be set to 1.
In timer pause state, the interval value register can be modified.
If the timer is started again, and the Software hope the current
value register to down-count from the new interval value, the
reload bit and the enable bit should be set to 1 at the same time.