Allwinner A20 - Page 145

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 145 / 812
Offset: 0x70
Register Name:HS_TMR3_CTRL_REG
Bit
Read/
Write
Default/Hex
Description
High Speed Timer 3 Reload.
0: No effect, 1: Reload High Speed Timer 3 Interval Value.
0
R/W
0x0
HS_TMR3_EN.
High Speed Timer 3 Enable.
0: Stop/Pause, 1: Start.
If the timer is started, it will reload the interval value to
internal register, and the current counter will count from
interval value to 0.
If the current counter does not reach the zero, the timer
enable bit is set to “0”, the current value counter will pause.
At least wait for 2 cycles, the start bit can be set to 1.
In timer pause state, the interval value register can be
modified. If the timer is started again, and the Software hope
the current value register to down-count from the new interval
value, the reload bit and the enable bit should be set to 1 at
the same time.
1.10.3.19. HS TIMER 3 INTERVAL VALUE LO REGISTER
Offset: 0x74
Register Name: HS_TMR3_INTV_LO_REG
Bit
Read/
Write
Default/Hex
Description
31:0
R/W
x
HS_TMR3_INTV_VALUE_LO.
High Speed Timer 3 Interval Value [31:0].
1.10.3.20. HS TIMER 3 INTERVAL VALUE HI REGISTER
Offset: 0x78
Register Name: HS_TMR3_INTV_HI_REG
Bit
Read/
Write
Default/Hex
Description
31:24
/
/
/
23:0
R/W
x
HS_TMR3_INTV_VALUE_HI.
High Speed Timer 3 Interval Value [55:32].
Note: the interval value register is a 56-bit register. When read or write the interval value, the Lo
register should be read or written first. And the Hi register should be written after the Lo register.