Allwinner A20 - Page 211

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 211 / 812
1:0
R/W
0x1
FILTER_TYPE.
Filter Type
00: 4/2
01: 5/3
10: 8/4
11: 16/8
1.15.7.5. TP INTERRUPT& FIFO CONTROL REGISTER
Offset: 0x10
Register Name: TP_INT
Bit
Read/
Write
Default/
Hex
Description
0x0000_0F00
31:19
/
/
/
18
R/W
0x0
TEMP_IRQ_EN.
Temperature IRQ Enable
0: Disable
1: Enable
17
R/W
0x0
TP_OVERRUN_IRQ_EN.
TP FIFO Over Run IRQ Enable
0: Disable
1: Enable
16
R/W
0x0
TP_DATA_IRQ_EN.
TP FIFO Data Available IRQ Enable
0: Disable
1: Enable
15:14
/
/
/
13
R/W
0x0
TP_DATA_XY_CHANGE.
TP FIFO X,Y Data interchange Function Select
0: Disable
1: Enable
12:8
R/W
0xF
TP_FIFO_TRIG_LEVEL.
TP FIFO Data Available Trigger Level
Interrupt and DMA request trigger level for TP or Auxiliary ADC
Trigger Level = TXTL + 1
7
R/W
0x0
TP_DATA_DRQ_EN.
TP FIFO Data Available DRQ Enable