Allwinner A20 - Page 212

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 212 / 812
Offset: 0x10
Register Name: TP_INT
Bit
Read/
Write
Default/
Hex
Description
0x0000_0F00
0: Disable
1: Enable
6:5
/
/
/
4
R/W
0x0
TP_FIFO_FLUSH.
TP FIFO Flush
Write ‘1’ to flush TX FIFO, self clear to ‘0’
3:2
/
/
/
1
R/W
0x0
TP_UP_IRQ_EN.
Touch Panel Last Touch (Stylus Up) IRQ Enable
0: Disable
1: Enable
0
R/W
0x0
TP_DOWN_IRQ_EN.
Touch Panel First Touch (Stylus Down) IRQ Enable
0: Disable
1: Enable
1.15.7.6. TP INTERRUPT& FIFO STATUS REGISTER
Offset: 0x14
Register Name: TP_FIFOCS
Bit
Read/
Write
Default/
Hex
Description
31:19
/
/
/
18
R/W
0x0
TEMP_IRQ_PENDING.
Temperature IRQ Pending
0: No Pending IRQ
1: FIFO Overrun Pending IRQ
Write ‘1’ to clear this interrupt or automatic clear if interrupt
condition fails
17
R/W
0x0
FIFO_OVERRUN_PENDING.
TP FIFO Over Run IRQ pending
0: No Pending IRQ
1: FIFO Overrun Pending IRQ
Write ‘1’ to clear this interrupt or automatic clear if interrupt
condition fails