Allwinner A20 - Page 223

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 223 / 812
Offset: 0x44
Register Name: SS_FCSR
Default Value: 0x6000_0F0F
Bit
Read/Write
Default
Description
15:13
/
/
/
12:8
R/W
0xF
RXFIFO_INT_TRIG_LEVEL
RX FIFO Empty Trigger Level
Interrupt and DMA request trigger level for RXFIFO normal
condition
Trigger Level = RXTL + 1
Notes: RX FIFO is used for input the data.
7:5
/
/
/
4:0
R/W
0xF
TXFIFO_INT_TRIG_LEVEL
TX FIFO Trigger Level
Interrupt and DMA request trigger level for TXFIFO normal
condition
Trigger Level = TXTL + 1
Notes: TX FIFO is used for output the result data.
1.16.4.6. SECURITY SYSTEM INTERRUPT CONTROL/ STATUS REGISTER
Offset: 0x48
Register Name: SS_ICSR
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:11
/
/
/
10
R/W
0
RXFIFO_EMP_PENDING_BIT
RX FIFO Empty Pending bit
0: No pending
1: RX FIFO Empty pending
Notes: Write ‘1’ to clear or automatic clear if interrupt condition
fails.
9
/
/
/
8
R/W
0
TXFIFO_AVA_PENDING_BIT
TX FIFO Data Available Pending bit
0: No TX FIFO pending
1: TX FIFO pending
Notes: Write ‘1’ to clear or automatic clear if interrupt condition
fails.