Allwinner A20 - Page 224

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 224 / 812
Offset: 0x48
Register Name: SS_ICSR
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
7:5
/
/
/
4
R/W
0
DRA_ENABLE
DRQ Enable
0: Disable DRQ (CPU polling mode)
1: Enable DRQ (DMA mode)
3
/
/
/
2
R/W
0
RXFIFO_EMP_INT_ENABLE
RX FIFO Empty Interrupt Enable
0: Disable
1: Enable
Notes: If it is set to ‘1’, when the number of empty room is
great or equal (>=) the preset threshold, the interrupt is trigger
and the correspond flag is set.
1
/
/
/
0
R/W
0
TXFIFO_AVA_INT_ENABLE
TX FIFO Data Available Interrupt Enable
0: Disable
1: Enable
Notes: If it is set to ‘1’, when available data number is great or
equal (>=) the preset threshold, the interrupt is trigger and the
correspond flag is set.
1.16.4.7. SECURITY SYSTEM MESSAGE DIGEST[N] REGISTER
Offset: 0x4C +4*n
Register Name: SS_MD[n]
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:0
R
0
SS_MID_DATA
SHA1/ MD5 Message digest MD[n] for SHA1/MD5 (n= 0~4)
1.16.4.8. SECURITY SYSTEM CTS LENGTH REGISTER
Offset: 0x60
Register Name: SS_CTS_LEN
Default Value: 0x0000_0000