Allwinner A20 - Page 241

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 241 / 812
Offset: 0x00
Register Name: PA_CFG0
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
010: ERXD3 011: SPI1_CS0
100: UART2_RTS 101: GRXD3
110: Reserved 111: Reserved
1.19.4.2. PA CONFIGURE REGISTER 1
Offset: 0x04
Register Name: PA_CFG1
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31
/
/
/
30:28
R/W
0
PA15_SELECT
000: Input 001: Output
010: ECRS 011: UART7_RX
100: UART1_DSR 101: GTXCK/ECRS
110: I2S1_LRCK 111: Reserved
27
/
/
/
26:24
R/W
0
PA14_SELECT
000: Input 001: Output
010:ETXCK 011: UART7_TX
100: UART1_DTR 101: GNULL/ETXCK
110: I2S1_BCLK 111: Reserved
23
/
/
/
22:20
R/W
0
PA13_SELECT
000: Input 001: Output
010:ETXEN 011: UART6_RX
100: UART1_CTS 101: GTXCTL/ETXEN
110: Reserved 111: Reserved
19
/
/
/
18:16
R/W
0
PA12_SELECT
000: Input 001: Output
010:EMDIO 011: UART6_TX
100: UART1_RTS 101: GMDIO