Allwinner A20 - Page 242

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 242 / 812
Offset: 0x04
Register Name: PA_CFG1
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
110: Reserved 111: Reserved
15
/
/
/
14:12
R/W
0
PA11_SELECT
000: Input 001: Output
010: EMDC 011: Reserved
100: UART1_RX 101: GMDC
110: Reserved 111: Reserved
11
/
/
/
10:8
R/W
0
PA10_SELECT
000: Input 001: Output
010:ERXDV 011: Reserved
100: UART1_TX 101: GRXCTL/ERXDV
110: Reserved 111: Reserved
7
/
/
/
6:4
R/W
0
PA9_SELECT
000: Input 001: Output
010: ERXERR 011: SPI3_CS1
100: Reserved 101: GNULL/ERXERR
110: I2S1_MCLK 111: Reserved
3
/
/
/
2:0
R/W
0
PA8_SELECT
000: Input 001: Output
010:ERXCK 011: SPI3_MISO
100: Reserved 101: GRXCK
110: Reserved 111: Reserved
1.19.4.3. PA CONFIGURE REGISTER 2
Offset: 0x08
Register Name: PA_CFG2
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:7
/
/
/