Allwinner A20 - Page 264

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 264 / 812
Offset: 0x74
Register Name: PD_CFG2
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
2:0
R/W
0
PD16_SELECT
000: Input 001: Output
010: LCD0_D16 011: LVDS1_VPC
100: Reserved 101: Reserved
110: Reserved 111: Reserved
1.19.4.31. PD CONFIGURE REGISTER 3
Offset: 0x78
Register Name: PD_CFG3
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:15
/
/
/
14:12
R/W
0
PD27_SELECT
000: Input 001: Output
010: LCD0_ VSYNC 011: SMC_SDA
100: Reserved 101: Reserved
110: Reserved 111: Reserved
11
/
/
Reserved
10:8
R/W
0
PD26_SELECT
000: Input 001: Output
010: LCD0_ HSYNC 011: SMC_SLK
100: Reserved 101: Reserved
110: Reserved 111: Reserved
7
/
/
/
6:4
R/W
0
PD25_SELECT
000: Input 001: Output
010: LCD0_ DE 011: SMC_RST
100: Reserved 101: Reserved
110: Reserved 111: Reserved
3
/
/
/
2:0
R/W
0
PD24_SELECT
000: Input 001: Output