Allwinner A20 - Page 265

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 265 / 812
Offset: 0x78
Register Name: PD_CFG3
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
010: LCD0_CLK 011: SMC_VCCEN
100: Reserved 101: Reserved
110: Reserved 111: Reserved
1.19.4.32. PD DATA REGISTER
Offset: 0x7C
Register Name: PD_DAT
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:28
/
/
/
27:0
R/W
0
PD_DAT
If the port is configured as input, the corresponding bit is the
pin state. If the port is configured as output, the pin state is the
same as the corresponding bit. The read bit value is the value
setup by software. If the port is configured as functional pin,
the undefined value will be read.
1.19.4.33. PD MULTI-DRIVING REGISTER 0
Offset: 0x80
Register Name: PD_DRV0
Default Value: 0x5555_5555
Bit
Read/Write
Default
Description
[2i+1:2i]
(i=0~15)
R/W
0x1
PD_DRV
PD[n] Multi-Driving Select (n = 0~15)
00: Level 0 01: Level 1
10: Level 2 11: Level 3
1.19.4.34. PD MULTI-DRIVING REGISTER 1
Offset: 0x84
Register Name: PD_DRV1
Default Value: 0x0055_5555