Allwinner A20 - Page 275

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 275 / 812
1.19.4.55. PG CONFIGURE REGISTER 0
Offset: 0xD8
Register Name: PG_CFG0
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31
/
/
/
30:28
R/W
0
PG7_SELECT
000: Input 001: Output
010: TS1_D3 011: CSI1_D3
100: UART3_RX 101: CSI0_D11
110: Reserved 111: Reserved
27
/
/
/
26:24
R/W
0
PG6_SELECT
000: Input 001: Output
010: TS1_D2 011: CSI1_D2
100: UART3_TX 101: CSI0_D10
110: Reserved 111: Reserved
23
/
/
/
22:20
R/W
0
PG5_SELECT
000: Input 001: Output
010: TS1_D1 011: CSI1_D1
100: SDC1_D3 101: CSI0_D9
110: Reserved 111: Reserved
19
/
/
/
18:16
R/W
0
PG4_SELECT
000: Input 001: Output
010:TS1_D0 011: CSI1_D0
100: SDC1_D2 101: CSI0_D8
110: Reserved 111: Reserved
15
/
/
/
14:12
R/W
0
PG3_SELECT
000: Input 001: Output
010: TS1_DVLD 011: CSI1_VSYNC
100: SDC1_D1 101: Reserved