Allwinner A20 - Page 276

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 276 / 812
Offset: 0xD8
Register Name: PG_CFG0
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
110: Reserved 111: Reserved
11
/
/
/
10:8
R/W
0
PG2_SELECT
000: Input 001: Output
010: TS1_SYNC 011: CSI1_HSYNC
100: SDC1_D0 101: Reserved
110: Reserved 111: Reserved
7
/
/
/
6:4
R/W
0
PG1_SELECT
000: Input 001: Output
010: TS1_ERR 011: CSI1_CK
100: SDC1_CLK 101: Reserved
110: Reserved 111: Reserved
3
/
/
/
2:0
R/W
0
PG0_SELECT
000: Input 001: Output
010: TS1_CLK 011: CSI1_PCK
100: SDC1_CMD 101: Reserved
110: Reserved 111: Reserved
1.19.4.56. PG CONFIGURE REGISTER 1
Offset: 0xDC
Register Name: PG_CFG1
Default Value: 0x0000_0000
Bit
Read/Write
Default
Description
31:15
/
/
/
14:12
R/W
0
PG11_SELECT
000: Input 001: Output
010: TS1_D7 011: CSI1_D7
100: UART4_RX 101: CSI0_D15
110: Reserved 111: Reserved
11
/
/
/