Allwinner A20 - Page 28

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 28 / 812
Offset: 0x184
Register Name: GENER_CTRL_REG
Bit
Read/
Write
Default/Hex
Description
Disables write access to some secure GIC registers.
7:6
/
/
/
5
R/W
0x1
L2_RST.
L2 Reset.(SCU global reset)
0: Apply reset to shared L2 memory system controller.
1: Do not apply reset to shared L2 memory system controller.
4
R/W
0x0
L2_RST_DISABLE.
Disable automatic L2 cache invalidate at reset:
0: L2 cache is reset by hardware.
1: L2 cache is not reset by haredware.
3:2
/
/
/
1:0
R/W
0x0
L1_RST_DISABLE.
L1 Reset Disable[1:0].
0: L1 cache is reset by hardware.
1: L1 cache is not reset by hardware.
1.4.3.8. EVENT INPUT REGISTER(DEFAULT : 0X00000000)
Offset: 0x190
Register Name: EVENT_IN
Bit
Read/
Write
Default/Hex
Description
31:1
/
/
/.
0
R/W
0x0
EVENT_IN.
Event input that can wake-up CPU0/1 from WFE standby
mode.
1.4.3.9. PRIVATE REGISTER (DEFAULT: 0X00000000)
Offset: 0x1A4
Register Name: PRIVATE_REG
Bit
Read/
Write
Default/Hex
Description
31:0
R/W
0x0