Allwinner A20 - Page 325

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 325 / 812
Offset: 0x88
Register Name: MP_SCAHORFCT_REG
Bit
Read/W
rite
Default/He
x
Description
The input width is the memory block width of respective iDMA
channel.
3.1.4.16. SCALER VERTICAL SCALING FACTOR REGISTER
Offset: 0x8C
Register Name: MP_SCAVERFCT_REG
Bit
Read/
Write
Default/Hex
Description
31:24
/
/
/
23:16
R/W
0
SCA_VERINTFCT
The integer part of the vertical scaling ratio
the vertical scaling ratio = input height/output height
15:00
R/W
0
SCA_VERFRAFCT
The fractional part of the vertical scaling ratio
the vertical scaling ratio = input height /output height
The input height is the memory block height of respective iDMA
channel.
3.1.4.17. SCALER HORIZONTAL START PHASE SETTING REGISTER
Offset: 0x90
Register Name: MP_SCAHORPHASE_REG
Bit
Read/W
rite
Default/H
ex
Description
31:20
/
/
/
19:00
R/W
0
SCA_HORPHASE
Start phase in horizontal (complement)
This value equals to start phase * 2
16