Allwinner A20 - Page 326

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 326 / 812
3.1.4.18. SCALER VERTICAL START PHASE SETTING REGISTER
Offset: 0x94
Register Name: MP_SCAVERPHASE_REG
Bit
Read/W
rite
Default/He
x
Description
31:20
/
/
/
19:00
R/W
0
SCA_VERPHASE
Start phase in vertical (complement)
This value equals to start phase * 2
16
3.1.4.19. ROP CONTROL REGISTER
Offset: 0xB0
Register Name: MP_ROPCTL_REG
Bit
Read/W
rite
Default/H
ex
Description
31:16
/
/
/
15:14
R/W
0
ROP_ALPHABYPASSSEL
ROP output Alpha channel selection
0: channel 0
1: channel 1
2: channel 2
3:reserved
Note: the bit is only valid in by-pass mode of Alpha channel
13:12
R/W
0
ROP_REDBYPASSSEL
ROP output Red channel selection
0: channel 0
1: channel 1
2: channel 2
3:reserved
Note: the bit is only valid in by-pass mode of Red channel
11:10
R/W
0
ROP_GREENBYPASSSEL
ROP output Green channel selection
0: channel 0
1: channel 1