Allwinner A20 - Page 328

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 328 / 812
Offset: 0xB0
Register Name: MP_ROPCTL_REG
Bit
Read/W
rite
Default/H
ex
Description
table setting register’ will be selected.
----In ROP3 mode, the channel 3 data will by-pass the ROP
module.
----In ROP3 mode, the channel 3 data will direct to Alpha/CK
module.
----In ROP4 mode, the respective input DMA channel fill color of
channel 3 will transfer to Alpha/CK module.
3.1.4.20. ROP CHANNEL 3 INDEX 0 CONTROL TABLE SETTING REGISTER
Offset: 0xB8
Register Name: MP_ROPIDX0CTL_REG
Bit
Read/W
rite
Default/H
ex
Description
31:16
/
/
/
15
R/W
0
NOD7_CTL
Index 0 node7 setting ( channel 0’ and channel 1’ and channel
2’ mix not logic )
0:by-pass
1:not
14:11
R/W
0
NOD6_CTL
Index 0 node6 setting ( channel 0’ and channel 1’ and channel
2’ mix logic )
0:and
1:or
2:xor
3:add in byte
4:add in word (32bit)
5:multiply in byte
6:multiply in word (32bit)
7:channel 0’ mix channel 1’ then sub channel 2’ in byte
8:channel 0’ mix channel 1’ then sub channel 2’ in word (32bit)
Other: Reserved
10
R/W
0
NOD5_CTL
Index 0 node5 setting ( channel 0’ and channel 1’ mix not logic )
0:by-pass
1:not