Allwinner A20 - Page 333

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 333 / 812
Offset: 0xC0
Register Name: MP_ALPHACKCTL_REG
Bit
Read/W
rite
Default/
Hex
Description
condition, if it is true, the low priority layer pass.
2: color key mode, using the low priority layer as matching
condition, if it is true, the high priority layer pass.
3: Reserved
0
R/W
0
ALPHACK_EN
Enable control
0: the ROP data will by-pass the alpha/ck module
1: enable
Note: if the module is disabled, the data of channel 3 will be
ignored, and only the ROP data will pass through to CSC2
module.
3.1.4.23. COLOR KEY MIN COLOR REGISTER
Offset: 0xC4
Register Name: MP_CKMIN_REG
Bit
Read/W
rite
Default/
Hex
Description
31:24
/
/
/
23:16
R/W
0
CKMIN_R
Red
15:8
R/W
0
CKMIN_G
Green
7:0
R/W
0
CKMIN_B
Blue
3.1.4.24. COLOR KEY MAX COLOR REGISTER
Offset: 0xC8
Register Name: MP_CKMAX_REG
Bit
Read/W
rite
Default/
Hex
Description
31:24
/
/
/
23:16
R/W
0
CKMAX_R