Allwinner A20 - Page 363

A20 User Manual (Revision 1.2) Copyright © 2013 Allwinner Technology Co., Ltd. All Rights Reserved. Page 363 / 812
Offset Address: 0X0004
Register Name: CSI0_CFG_REG
Bit
Read/W
rite
Default/
Hex
Description
11: reserved
09:08
R/W
2
INPUT_SEQ
Input data sequence, only valid for YUV422 mode.
07:03
/
/
/
02
R/W
1
VREF_POL
Vref polarity
0: negative
1: positive
This register is not apply to CCIR656 interface.
01
R/W
0
HERF_POL
Href polarity
0: negative
1: positive
This register is not apply to CCIR656 interface.
00
R/W
1
CLK_POL
Data clock type
0: active in falling edge
1: active in rising edge
4.1.5.3. CSI CAPTURE CONTROL REGISTER
Offset Address: 0X0008
Register Name: CSI0_CAP_REG
Bit
Read/W
rite
Default/H
ex
Description
31:02
/
/
/
01
R/W
0
VCAP_ON
Video capture control: Capture the video image data stream.
0: Disable video capture
If video capture is in progress, the CSI stops capturing image
data at the end of the current frame, and all of the current frame
data is wrote to output FIFO.
1: Enable video capture
The CSI starts capturing image data at the start of the next
frame.